| /Zephyr-Core-3.5.0/dts/bindings/can/ |
| D | st,stm32-bxcan.yaml | 1 description: STM32 CAN controller
3 compatible: "st,stm32-bxcan"
5 include: [can-controller.yaml, pinctrl-device.yaml]
8 reg:
17 pinctrl-0:
20 pinctrl-names:
23 master-can-reg:
25 description: master can reg when different from current instance
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| /Zephyr-Core-3.5.0/dts/bindings/misc/ |
| D | nxp,s32-emios.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 have internal counter that either can be used independently or used
8 as a reference timebase (master bus) for other channels.
10 compatible: "nxp,s32-emios"
15 reg:
21 interrupt-names:
27 clock-divider:
33 internal-cnt:
39 child-binding:
40 child-binding:
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| /Zephyr-Core-3.5.0/dts/bindings/spi/ |
| D | nordic,nrf-spi-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: [spi-controller.yaml, pinctrl-device.yaml]
9 reg:
15 pinctrl-0:
18 max-frequency:
22 Maximum data rate the SPI peripheral can be driven at, in Hz. This
25 overrun-character:
33 easydma-maxcnt-bits:
40 wake-gpios:
41 type: phandle-array
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| /Zephyr-Core-3.5.0/dts/arm/st/f4/ |
| D | stm32f446.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9 #include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
14 compatible = "st,stm32f412-plli2s-clock";
19 compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
22 compatible = "st,stm32-i2s";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 reg = <0x40013000 0x400>;
30 dma-names = "tx", "rx";
[all …]
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| D | stm32f412.dtsi | 2 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
4 * SPDX-License-Identifier: Apache-2.0
9 /delete-node/ &dac1;
10 /delete-node/ &rng;
15 #clock-cells = <0>;
16 compatible = "st,stm32f412-plli2s-clock";
22 compatible = "st,stm32f412", "st,stm32f4", "simple-bus";
24 pinctrl: pin-controller@40020000 {
25 reg = <0x40020000 0x1c00>;
28 compatible = "st,stm32-gpio";
[all …]
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| D | stm32f405.dtsi | 5 * SPDX-License-Identifier: Apache-2.0
16 compatible = "st,stm32f405", "st,stm32f4", "simple-bus";
18 pinctrl: pin-controller@40020000 {
19 reg = <0x40020000 0x2400>;
22 compatible = "st,stm32-gpio";
23 gpio-controller;
24 #gpio-cells = <2>;
25 reg = <0x40021400 0x400>;
30 compatible = "st,stm32-gpio";
31 gpio-controller;
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/i2c/ |
| D | atmel,sam-i2c-twim.yaml | 1 # Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
2 # SPDX-License-Identifier: Apache-2.0
7 The Atmel Two-wire Master Interface (TWIM) interconnects components on a
8 unique two-wire bus, made up of one clock line and one data line with speeds
9 of up to 3.4 Mbit/s, based on a byte-oriented transfer format. The TWIM is
10 always a bus master and can transfer sequential or single bytes. Multiple
11 master capability is supported. Arbitration of the bus is performed
20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
22 std-data-slew-lim = <0>;
[all …]
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| /Zephyr-Core-3.5.0/dts/arm/st/f1/ |
| D | stm32f105.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
11 /delete-node/ pll;
14 #clock-cells = <0>;
15 compatible = "st,stm32f105-pll-clock";
20 #clock-cells = <0>;
21 compatible = "st,stm32f105-pll2-clock";
28 compatible = "st,stm32f105", "st,stm32f1", "simple-bus";
30 flash-controller@40022000 {
32 erase-block-size = <DT_SIZE_K(2)>;
36 can1: can@40006400 {
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/mr_canhubk3/ |
| D | mr_canhubk3.dts | 4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "mr_canhubk3-pinctrl.dtsi"
16 model = "NXP MR-CANHUBK3";
24 zephyr,code-partition = &code_partition;
26 zephyr,shell-uart = &lpuart2;
27 zephyr,flash-controller = &mx25l6433f;
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | st,stm32f1-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32f1-pinctrl"
17 reg:
20 swj-cfg:
24 - "full"
25 - "no-njtrst"
26 - "jtag-disable"
[all …]
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
17 reg:
20 remap-pa11:
25 remap-pa12:
30 remap-pa11-pa12:
35 child-binding:
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| /Zephyr-Core-3.5.0/include/zephyr/drivers/ |
| D | espi.h | 4 * SPDX-License-Identifier: Apache-2.0
44 *+----------------------------------------------------------------------+
46 *| eSPI host +-------------+ |
47 *| +-----------+ | Power | +----------+ |
49 *| +------------+ |processor | | controller | | sources | |
50 *| | SPI flash | +-----------+ +-------------+ +----------+ |
52 *| +------------+ | | | |
53 *| | | | +--------+ +---------------+ |
55 *| | | +-----+ +--------+ +----------+ +----v-----+ |
58 *| | | | +--------+ +----------+ +----------+ |
[all …]
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| /Zephyr-Core-3.5.0/drivers/i2c/ |
| D | i2c_sifive.c | 4 * SPDX-License-Identifier: Apache-2.0
18 #include "i2c-priv.h"
22 #define I2C_REG(config, reg) ((mem_addr_t) ((config)->base + reg)) argument
23 #define IS_SET(config, reg, value) (sys_read8(I2C_REG(config, reg)) & (value)) argument
73 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_busy()
82 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_send_addr()
103 return -EIO; in i2c_sifive_send_addr()
113 const struct i2c_sifive_cfg *config = dev->config; in i2c_sifive_write_msg()
123 for (uint32_t i = 0; i < msg->len; i++) { in i2c_sifive_write_msg()
128 /* Put data in transmit reg */ in i2c_sifive_write_msg()
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| D | i2c_dw.c | 1 /* dw_i2c.c - I2C file for Design Ware */
5 * Copyright (c) 2022 Andrei-Edward Popa
7 * SPDX-License-Identifier: Apache-2.0
49 #include "i2c-priv.h"
59 uint32_t reg; in i2c_dw_enable_idma() local
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
66 reg = read_dma_cr(reg_base); in i2c_dw_enable_idma()
67 reg &= ~DW_IC_DMA_ENABLE; in i2c_dw_enable_idma()
68 write_dma_cr(reg, reg_base); in i2c_dw_enable_idma()
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
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| D | i2c_cc32xx.c | 4 * SPDX-License-Identifier: Apache-2.0
29 #include "i2c-priv.h"
44 (((const struct i2c_cc32xx_config *const)(dev)->config)->base)
48 * are no interrupts received which can distinguish between read and write
53 * I2C API without having to re-read I2C registers.
91 return -EINVAL; in i2c_cc32xx_configure()
95 return -EINVAL; in i2c_cc32xx_configure()
106 return -EINVAL; in i2c_cc32xx_configure()
118 struct i2c_cc32xx_data *data = dev->data; in i2c_cc32xx_prime_transfer()
122 data->msg = *msg; in i2c_cc32xx_prime_transfer()
[all …]
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| /Zephyr-Core-3.5.0/dts/bindings/memory-controllers/ |
| D | atmel,sam-smc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 The SMC allows to interface with static-memory mapped external devices such as
10 The SMC is clocked through the Master Clock (MCK) which is controlled by the
13 The SMC controller can have up to 4 children defining the connected external
14 memory devices. The reg property is set to the device's Chip Select.
19 pinctrl-0 = <&smc_default>;
20 pinctrl-names = "default";
23 reg = <0>;
25 atmel,smc-write-mode = "nwe";
26 atmel,smc-read-mode = "nrd";
[all …]
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| /Zephyr-Core-3.5.0/drivers/gpio/ |
| D | gpio_mcp23s17.c | 4 * SPDX-License-Identifier: Apache-2.0
79 static int read_port_regs(const struct device *dev, uint8_t reg, in read_port_regs() argument
82 const struct mcp23s17_config *config = dev->config; in read_port_regs()
87 uint8_t buffer_tx[4] = { addr, reg, 0, 0 }; in read_port_regs()
112 ret = spi_transceive_dt(&config->bus, &tx, &rx); in read_port_regs()
120 LOG_DBG("MCP23S17: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X", in read_port_regs()
121 reg, (*buf & 0xFF), (reg + 1), (*buf >> 8)); in read_port_regs()
126 static int write_port_regs(const struct device *dev, uint8_t reg, in write_port_regs() argument
129 const struct mcp23s17_config *config = dev->config; in write_port_regs()
133 LOG_DBG("MCP23S17: Write: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X", in write_port_regs()
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/96b_argonkey/doc/ |
| D | index.rst | 13 family products. It can also be used as a standalone board.
26 - STM32F412CG in UFQFPN48 package
27 - ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
28 - 100 MHz max CPU frequency
29 - 1.8V work voltage
30 - 1024 KB Flash
31 - 256 KB SRAM
32 - On board sensors:
34 - Humidity: STMicro HTS221
35 - Temperature/Pressure: STMicro LPS22HB
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_l433rc_p/doc/ |
| D | index.rst | 9 The Nucleo L433RC board features an ARM Cortex-M4 based STM32L433RC MCU
13 - STM32 microcontroller in LQFP64 package
14 - Arduino Uno V3 connectivity
15 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector
16 - Flexible board power supply:
18 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
19 - Power management access point
21 - Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4)
22 - One push-button: RESET
28 More information about the board can be found at the `Nucleo L433RC-P website`_.
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_l432kc/doc/ |
| D | index.rst | 9 The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU
13 - STM32 microcontroller in UFQFPN32 package
14 - Arduino Uno V3 connectivity
15 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector
16 - Flexible board power supply:
18 - USB VBUS or external source(3.3V, 5V, 7 - 12V)
19 - Power management access point
21 - Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3)
22 - One push-button: RESET
28 More information about the board can be found at the `Nucleo L432KC website`_.
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/nucleo_wb55rg/doc/ |
| D | nucleo_wb55rg.rst | 9 The Nucleo WB55RG board is a multi-protocol wireless and ultra-low-power device
10 embedding a powerful and ultra-low-power radio compliant with the Bluetooth®
11 Low Energy (BLE) SIG specification v5.0 and with IEEE 802.15.4-2011.
14 - STM32 microcontroller in VFQFPN68 package
15 - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.0 and
16 IEEE 802.15.4-2011 PHY and MAC
17 - Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
18 - Three user LEDs
19 - Board connector: USB user with Micro-B
20 - Two types of extension resources:
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/disco_l475_iot1/doc/ |
| D | index.rst | 3 ST Disco L475 IOT01 (B-L475E-IOT01A)
9 The B-L475E-IOT01A Discovery kit for IoT node allows users to develop
12 low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based
17 - 64-Mbit Quad-SPI (Macronix) Flash memory
18 - Bluetooth |reg| V4.1 module (SPBTLE-RF)
19 - Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915)
20 - Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant)
21 - Dynamic NFC tag based on M24SR with its printed NFC antenna
22 - 2 digital omni-directional microphones (MP34DT01)
23 - Capacitive digital sensor for relative humidity and temperature (HTS221)
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/blackpill_f401cc/doc/ |
| D | index.rst | 9 The WeAct Black Pill V1.2 Board is an extremely low cost and bare-bones
11 This is the 48-pin variant of the STM32F401x series,
13 `here <stm32-base-board-page_>`_ and on `WeAct Github`_.
15 .. image:: img/blackpill-v3.jpg
25 - STM32F401CCU6 in UFQFPN48 package
26 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
27 - 84 MHz max CPU frequency
28 - VDD from 1.7 V to 3.6 V
29 - 256 KB Flash
30 - 64 KB SRAM
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/stm32l476g_disco/doc/ |
| D | index.rst | 9 The STM32L476G Discovery board features an ARM Cortex-M4 based STM32L476VG MCU
14 - STM32L476VGT6 microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 pac…
15 - On-board ST-LINK/V2-1 supporting USB re-enumeration capability
16 - Three different interfaces supported on USB:
18 - Virtual com port
19 - Mass storage
20 - Debug port
22 - LCD 24 segments, 4 commons in DIP 28 package
23 - Seven LEDs:
25 - LD1 (red/green) for USB communication
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/blackpill_f401ce/doc/ |
| D | index.rst | 9 The WeAct Black Pill V3.0 Board is an extremely low cost and bare-bones
11 This is the 48-pin variant of the STM32F401x series,
13 `here <stm32-base-board-page_>`_ and on `WeAct Github`_.
15 .. image:: img/blackpill-v3.jpg
25 - STM32F401CEU6 in UFQFPN48 package
26 - ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
27 - 84 MHz max CPU frequency
28 - VDD from 1.7 V to 3.6 V
29 - 512 KB Flash
30 - 96 KB SRAM
[all …]
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