1 /*
2 * Copyright (c) 2017, Texas Instruments Incorporated
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /* The logic here is adapted from SimpleLink SDK's I2CCC32XX.c module. */
8
9 #define DT_DRV_COMPAT ti_cc32xx_i2c
10
11 #include <zephyr/kernel.h>
12 #include <errno.h>
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <soc.h>
16
17 /* Driverlib includes */
18 #include <inc/hw_memmap.h>
19 #include <inc/hw_common_reg.h>
20 #include <driverlib/rom.h>
21 #include <driverlib/rom_map.h>
22 #include <driverlib/i2c.h>
23
24 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
25 #include <zephyr/logging/log.h>
26 #include <zephyr/irq.h>
27 LOG_MODULE_REGISTER(i2c_cc32xx);
28
29 #include "i2c-priv.h"
30
31 #define I2C_MASTER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START
32 #define I2C_MASTER_CMD_BURST_RECEIVE_STOP \
33 I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
34 #define I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT
35
36 #define I2C_SEM_MASK \
37 COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M
38 #define I2C_SEM_TAKE \
39 COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S
40
41 #define IS_I2C_MSG_WRITE(flags) ((flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE)
42
43 #define DEV_BASE(dev) \
44 (((const struct i2c_cc32xx_config *const)(dev)->config)->base)
45
46
47 /* Since this driver does not explicitly enable the TX/RX FIFOs, there
48 * are no interrupts received which can distinguish between read and write
49 * completion.
50 * So, we need the READ and WRITE state flags to determine whether the
51 * completed transmission was started as a write or a read.
52 * The ERROR flag is used to convey error status from the ISR back to the
53 * I2C API without having to re-read I2C registers.
54 */
55 enum i2c_cc32xx_state {
56 /* I2C was primed for a write operation */
57 I2C_CC32XX_WRITE_MODE,
58 /* I2C was primed for a read operation */
59 I2C_CC32XX_READ_MODE,
60 /* I2C error occurred */
61 I2C_CC32XX_ERROR = 0xFF
62 };
63
64 struct i2c_cc32xx_config {
65 uint32_t base;
66 uint32_t bitrate;
67 unsigned int irq_no;
68 const struct pinctrl_dev_config *pcfg;
69 };
70
71 struct i2c_cc32xx_data {
72 struct k_sem mutex;
73 struct k_sem transfer_complete;
74
75 volatile enum i2c_cc32xx_state state;
76
77 struct i2c_msg msg; /* Cache msg for transfer state machine */
78 uint16_t slave_addr; /* Cache slave address for ISR use */
79 };
80
81 static void configure_i2c_irq(const struct i2c_cc32xx_config *config);
82
83 #define I2C_CLK_FREQ(n) DT_PROP(DT_INST_PHANDLE(n, clocks), clock_frequency)
i2c_cc32xx_configure(const struct device * dev,uint32_t dev_config_raw)84 static int i2c_cc32xx_configure(const struct device *dev,
85 uint32_t dev_config_raw)
86 {
87 uint32_t base = DEV_BASE(dev);
88 uint32_t bitrate_id;
89
90 if (!(dev_config_raw & I2C_MODE_CONTROLLER)) {
91 return -EINVAL;
92 }
93
94 if (dev_config_raw & I2C_ADDR_10_BITS) {
95 return -EINVAL;
96 }
97
98 switch (I2C_SPEED_GET(dev_config_raw)) {
99 case I2C_SPEED_STANDARD:
100 bitrate_id = 0U;
101 break;
102 case I2C_SPEED_FAST:
103 bitrate_id = 1U;
104 break;
105 default:
106 return -EINVAL;
107 }
108
109 MAP_I2CMasterInitExpClk(base, I2C_CLK_FREQ(0), bitrate_id);
110
111 return 0;
112 }
113
i2c_cc32xx_prime_transfer(const struct device * dev,struct i2c_msg * msg,uint16_t addr)114 static void i2c_cc32xx_prime_transfer(const struct device *dev,
115 struct i2c_msg *msg,
116 uint16_t addr)
117 {
118 struct i2c_cc32xx_data *data = dev->data;
119 uint32_t base = DEV_BASE(dev);
120
121 /* Initialize internal counters and buf pointers: */
122 data->msg = *msg;
123 data->slave_addr = addr;
124
125 /* Start transfer in Transmit mode */
126 if (IS_I2C_MSG_WRITE(data->msg.flags)) {
127
128 /* Specify the I2C slave address */
129 MAP_I2CMasterSlaveAddrSet(base, addr, false);
130
131 /* Update the I2C state */
132 data->state = I2C_CC32XX_WRITE_MODE;
133
134 /* Write data contents into data register */
135 MAP_I2CMasterDataPut(base, *((data->msg.buf)++));
136
137 /* Start the I2C transfer in master transmit mode */
138 MAP_I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
139
140 } else {
141 /* Start transfer in Receive mode */
142 /* Specify the I2C slave address */
143 MAP_I2CMasterSlaveAddrSet(base, addr, true);
144
145 /* Update the I2C mode */
146 data->state = I2C_CC32XX_READ_MODE;
147
148 if (data->msg.len < 2) {
149 /* Start the I2C transfer in master receive mode */
150 MAP_I2CMasterControl(base,
151 I2C_MASTER_CMD_BURST_RECEIVE_START_NACK);
152 } else {
153 /* Start the I2C transfer in burst receive mode */
154 MAP_I2CMasterControl(base,
155 I2C_MASTER_CMD_BURST_RECEIVE_START);
156 }
157 }
158 }
159
i2c_cc32xx_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)160 static int i2c_cc32xx_transfer(const struct device *dev, struct i2c_msg *msgs,
161 uint8_t num_msgs, uint16_t addr)
162 {
163 struct i2c_cc32xx_data *data = dev->data;
164 int retval = 0;
165
166 /* Acquire the driver mutex */
167 k_sem_take(&data->mutex, K_FOREVER);
168
169 /* Iterate over all the messages */
170 for (int i = 0; i < num_msgs; i++) {
171
172 /* Begin the transfer */
173 i2c_cc32xx_prime_transfer(dev, msgs, addr);
174
175 /* Wait for the transfer to complete */
176 k_sem_take(&data->transfer_complete, K_FOREVER);
177
178 /* Return an error if the transfer didn't complete */
179 if (data->state == I2C_CC32XX_ERROR) {
180 retval = -EIO;
181 break;
182 }
183
184 /* Move to the next message */
185 msgs++;
186 }
187
188 /* Release the mutex */
189 k_sem_give(&data->mutex);
190
191 return retval;
192 }
193
i2c_cc32xx_isr_handle_write(uint32_t base,struct i2c_cc32xx_data * data)194 static void i2c_cc32xx_isr_handle_write(uint32_t base,
195 struct i2c_cc32xx_data *data)
196 {
197 /* Decrement write Counter */
198 data->msg.len--;
199
200 /* Check if more data needs to be sent */
201 if (data->msg.len) {
202
203 /* Write data contents into data register */
204 MAP_I2CMasterDataPut(base, *(data->msg.buf));
205 data->msg.buf++;
206
207 if (data->msg.len < 2) {
208 /* Everything has been sent, nothing to receive */
209 /* Send last byte with STOP bit */
210 MAP_I2CMasterControl(base,
211 I2C_MASTER_CMD_BURST_SEND_FINISH);
212 } else {
213 /*
214 * Either there is more data to be transmitted or some
215 * data needs to be received next
216 */
217 MAP_I2CMasterControl(base,
218 I2C_MASTER_CMD_BURST_SEND_CONT);
219
220 }
221 } else {
222 /*
223 * No more data needs to be sent, so follow up with
224 * a STOP bit.
225 */
226 MAP_I2CMasterControl(base,
227 I2C_MASTER_CMD_BURST_RECEIVE_STOP);
228 }
229 }
230
i2c_cc32xx_isr_handle_read(uint32_t base,struct i2c_cc32xx_data * data)231 static void i2c_cc32xx_isr_handle_read(uint32_t base,
232 struct i2c_cc32xx_data *data)
233 {
234
235 /* Save the received data */
236 *(data->msg.buf) = MAP_I2CMasterDataGet(base);
237 data->msg.buf++;
238
239 /* Check if any data needs to be received */
240 data->msg.len--;
241 if (data->msg.len) {
242 if (data->msg.len > 1) {
243 /* More data to be received */
244 MAP_I2CMasterControl(base,
245 I2C_MASTER_CMD_BURST_RECEIVE_CONT);
246 } else {
247 /*
248 * Send NACK because it's the last byte to be received
249 */
250 MAP_I2CMasterControl(base,
251 I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK);
252 }
253 } else {
254 /*
255 * No more data needs to be received, so follow up with a
256 * STOP bit
257 */
258 MAP_I2CMasterControl(base,
259 I2C_MASTER_CMD_BURST_RECEIVE_STOP);
260 }
261 }
262
i2c_cc32xx_isr(const struct device * dev)263 static void i2c_cc32xx_isr(const struct device *dev)
264 {
265 uint32_t base = DEV_BASE(dev);
266 struct i2c_cc32xx_data *data = dev->data;
267 uint32_t err_status;
268 uint32_t int_status;
269
270 /* Get the error status of the I2C controller */
271 err_status = MAP_I2CMasterErr(base);
272
273 /* Get interrupt cause (from I2CMRIS (raw interrupt) reg): */
274 int_status = MAP_I2CMasterIntStatusEx(base, 0);
275
276 /* Clear interrupt source to avoid additional interrupts */
277 MAP_I2CMasterIntClearEx(base, int_status);
278
279 LOG_DBG("primed state: %d; err_status: 0x%x; int_status: 0x%x",
280 data->state, err_status, int_status);
281
282 /* Handle errors: */
283 if ((err_status != I2C_MASTER_ERR_NONE) ||
284 (int_status &
285 (I2C_MASTER_INT_ARB_LOST | I2C_MASTER_INT_TIMEOUT))) {
286
287 /* Set so API can report I/O error: */
288 data->state = I2C_CC32XX_ERROR;
289
290 if (!(err_status & (I2C_MASTER_ERR_ARB_LOST |
291 I2C_MASTER_ERR_ADDR_ACK))) {
292 /* Send a STOP bit to end I2C communications */
293 /*
294 * I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -and-
295 * I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
296 * have the same values
297 */
298 MAP_I2CMasterControl(base,
299 I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
300 }
301 /* Indicate transfer complete */
302 k_sem_give(&data->transfer_complete);
303
304 /* Handle Stop: */
305 } else if (int_status & I2C_MASTER_INT_STOP) {
306 /* Indicate transfer complete */
307 k_sem_give(&data->transfer_complete);
308
309 /* Handle (read or write) transmit complete: */
310 } else if (int_status & (I2C_MASTER_INT_DATA | I2C_MASTER_INT_START)) {
311 if (data->state == I2C_CC32XX_WRITE_MODE) {
312 i2c_cc32xx_isr_handle_write(base, data);
313 }
314 if (data->state == I2C_CC32XX_READ_MODE) {
315 i2c_cc32xx_isr_handle_read(base, data);
316 }
317 /* Some unanticipated H/W state: */
318 } else {
319 __ASSERT(1, "Unanticipated I2C Interrupt!");
320 data->state = I2C_CC32XX_ERROR;
321 k_sem_give(&data->transfer_complete);
322 }
323 }
324
i2c_cc32xx_init(const struct device * dev)325 static int i2c_cc32xx_init(const struct device *dev)
326 {
327 uint32_t base = DEV_BASE(dev);
328 const struct i2c_cc32xx_config *config = dev->config;
329 struct i2c_cc32xx_data *data = dev->data;
330 uint32_t bitrate_cfg;
331 int error;
332 uint32_t regval;
333
334 /* Enable the I2C module clocks and wait for completion:*/
335 MAP_PRCMPeripheralClkEnable(PRCM_I2CA0,
336 PRCM_RUN_MODE_CLK |
337 PRCM_SLP_MODE_CLK);
338 while (!MAP_PRCMPeripheralStatusGet(PRCM_I2CA0)) {
339 }
340
341 error = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
342 if (error < 0) {
343 return error;
344 }
345
346 k_sem_init(&data->mutex, 1, K_SEM_MAX_LIMIT);
347 k_sem_init(&data->transfer_complete, 0, K_SEM_MAX_LIMIT);
348
349 /* In case of app restart: disable I2C module, clear NVIC interrupt */
350 /* Note: this was done *during* pinmux setup in SimpleLink SDK. */
351 MAP_I2CMasterDisable(base);
352
353 /* Clear exception INT_I2CA0 */
354 MAP_IntPendClear((unsigned long)(config->irq_no + 16));
355
356 configure_i2c_irq(config);
357
358 /* Take I2C hardware semaphore. */
359 regval = HWREG(COMMON_REG_BASE);
360 regval = (regval & ~I2C_SEM_MASK) | (0x01 << I2C_SEM_TAKE);
361 HWREG(COMMON_REG_BASE) = regval;
362
363 /* Set to default configuration: */
364 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
365 error = i2c_cc32xx_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
366 if (error) {
367 return error;
368 }
369
370 /* Clear any pending interrupts */
371 MAP_I2CMasterIntClear(base);
372
373 /* Enable the I2C Master for operation */
374 MAP_I2CMasterEnable(base);
375
376 /* Unmask I2C interrupts */
377 MAP_I2CMasterIntEnable(base);
378
379 return 0;
380 }
381
382 static const struct i2c_driver_api i2c_cc32xx_driver_api = {
383 .configure = i2c_cc32xx_configure,
384 .transfer = i2c_cc32xx_transfer,
385 };
386
387
388 PINCTRL_DT_INST_DEFINE(0);
389
390 static const struct i2c_cc32xx_config i2c_cc32xx_config = {
391 .base = DT_INST_REG_ADDR(0),
392 .bitrate = DT_INST_PROP(0, clock_frequency),
393 .irq_no = DT_INST_IRQN(0),
394 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
395 };
396
397 static struct i2c_cc32xx_data i2c_cc32xx_data;
398
399 I2C_DEVICE_DT_INST_DEFINE(0, i2c_cc32xx_init, NULL,
400 &i2c_cc32xx_data, &i2c_cc32xx_config,
401 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,
402 &i2c_cc32xx_driver_api);
403
configure_i2c_irq(const struct i2c_cc32xx_config * config)404 static void configure_i2c_irq(const struct i2c_cc32xx_config *config)
405 {
406 IRQ_CONNECT(DT_INST_IRQN(0),
407 DT_INST_IRQ(0, priority),
408 i2c_cc32xx_isr, DEVICE_DT_INST_GET(0), 0);
409
410 irq_enable(config->irq_no);
411 }
412
