1/*
2 * Copyright (c) 2018 Philémon Jaermann
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <st/f4/stm32f401.dtsi>
8#include <zephyr/dt-bindings/clock/stm32f410_clock.h>
9#include <zephyr/dt-bindings/memory-controller/stm32-fmc-sdram.h>
10
11/ {
12	clocks {
13		plli2s: plli2s {
14			compatible = "st,stm32f412-plli2s-clock";
15		};
16	};
17
18	soc {
19		compatible = "st,stm32f446", "st,stm32f4", "simple-bus";
20
21		i2s1: i2s@40013000 {
22			compatible = "st,stm32-i2s";
23			#address-cells = <1>;
24			#size-cells = <0>;
25			reg = <0x40013000 0x400>;
26			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
27			interrupts = <35 5>;
28			dmas = <&dma2 3 3 0x400 0x3
29				&dma2 2 3 0x400 0x3>;
30			dma-names = "tx", "rx";
31			status = "disabled";
32		};
33
34		usart3: serial@40004800 {
35			compatible = "st,stm32-usart", "st,stm32-uart";
36			reg = <0x40004800 0x400>;
37			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
38			resets = <&rctl STM32_RESET(APB1, 18U)>;
39			interrupts = <39 0>;
40			status = "disabled";
41		};
42
43		uart4: serial@40004c00 {
44			compatible ="st,stm32-uart";
45			reg = <0x40004c00 0x400>;
46			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
47			resets = <&rctl STM32_RESET(APB1, 19U)>;
48			interrupts = <52 0>;
49			status = "disabled";
50		};
51
52		uart5: serial@40005000 {
53			compatible = "st,stm32-uart";
54			reg = <0x40005000 0x400>;
55			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
56			resets = <&rctl STM32_RESET(APB1, 20U)>;
57			interrupts = <53 0>;
58			status = "disabled";
59		};
60
61		can1: can@40006400 {
62			compatible = "st,stm32-bxcan";
63			reg = <0x40006400 0x400>;
64			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
65			interrupt-names = "TX", "RX0", "RX1", "SCE";
66			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
67			status = "disabled";
68			sample-point = <875>;
69		};
70
71		can2: can@40006800 {
72			compatible = "st,stm32-bxcan";
73			reg = <0x40006800 0x400>;
74			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
75			interrupt-names = "TX", "RX0", "RX1", "SCE";
76			/* also enabling clock for can1 (master instance) */
77			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
78			master-can-reg = <0x40006400>;
79			status = "disabled";
80			sample-point = <875>;
81		};
82
83		usbotg_fs: usb@50000000 {
84			num-bidir-endpoints = <6>;
85			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,
86				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
87		};
88
89		usbotg_hs: usb@40040000 {
90			compatible = "st,stm32-otghs";
91			reg = <0x40040000 0x40000>;
92			interrupts = <77 0>, <74 0>, <75 0>;
93			interrupt-names = "otghs", "ep1_out", "ep1_in";
94			num-bidir-endpoints = <9>;
95			ram-size = <4096>;
96			maximum-speed = "full-speed";
97			phys = <&otghs_fs_phy>;
98			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>,
99				 <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
100			status = "disabled";
101		};
102
103		backup_sram: memory@40024000 {
104			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
105			reg = <0x40024000 DT_SIZE_K(4)>;
106			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
107			zephyr,memory-region = "BACKUP_SRAM";
108			status = "disabled";
109		};
110
111		dac1: dac@40007400 {
112			compatible = "st,stm32-dac";
113			reg = <0x40007400 0x400>;
114			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
115			status = "disabled";
116			#io-channel-cells = <1>;
117		};
118
119		fmc: memory-controller@a0000000 {
120			compatible = "st,stm32-fmc";
121			reg = <0xa0000000 0x400>;
122			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
123			status = "disabled";
124
125			sdram: sdram {
126				compatible = "st,stm32-fmc-sdram";
127				#address-cells = <1>;
128				#size-cells = <0>;
129				status = "disabled";
130			};
131		};
132	};
133
134	die_temp: dietemp {
135		io-channels = <&adc1 18>;
136	};
137
138	otghs_fs_phy: otghs_fs_phy {
139		compatible = "usb-nop-xceiv";
140		#phy-cells = <0>;
141	};
142};
143