| /Zephyr-latest/drivers/ethernet/phy/ |
| D | phy_dm8806_priv.h | 4 * SPDX-License-Identifier: Apache-2.0
23 /* Link speed selection offset. */
28 /* 10 Mbit/s transfer speed with half duplex. */
30 /* 10 Mbit/s transfer speed with full duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
34 /* 100 Mbit/s transfer speed with full duplex. */
36 /* Speed and duplex mode status offset. */
38 /* Speed and duplex mode staus mask. */
40 /* Link status mask. */
120 /* Port 5 Force Speed control bit */
[all …]
|
| D | phy_mii.c | 2 * Copyright (c) 2021 IP-Logix Inc.
5 * SPDX-License-Identifier: Apache-2.0
39 /* Offset to align capabilities bits of 1000BASE-T Control and Status regs */
50 const struct phy_mii_dev_config *const cfg = dev->config; in phy_mii_reg_read()
52 /* if there is no mdio (fixed-link) it is not supported to read */ in phy_mii_reg_read()
53 if (cfg->mdio == NULL) { in phy_mii_reg_read()
54 return -ENOTSUP; in phy_mii_reg_read()
56 return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, value); in phy_mii_reg_read()
62 const struct phy_mii_dev_config *const cfg = dev->config; in phy_mii_reg_write()
64 /* if there is no mdio (fixed-link) it is not supported to write */ in phy_mii_reg_write()
[all …]
|
| D | phy_qualcomm_ar8031.c | 5 * Copyright (c) 2021 IP-Logix Inc.
8 * SPDX-License-Identifier: Apache-2.0
77 const struct qc_ar8031_config *config = dev->config; in qc_ar8031_read()
80 /* Make sure excessive bits 16-31 are reset */ in qc_ar8031_read()
84 ret = mdio_read(config->mdio_dev, config->addr, reg_addr, (uint16_t *)data); in qc_ar8031_read()
94 const struct qc_ar8031_config *config = dev->config; in qc_ar8031_write()
97 ret = mdio_write(config->mdio_dev, config->addr, reg_addr, (uint16_t)data); in qc_ar8031_write()
111 return -EIO; in qc_ar8031_mmd_set_device()
114 return -EIO; in qc_ar8031_mmd_set_device()
118 return -EIO; in qc_ar8031_mmd_set_device()
[all …]
|
| D | phy_microchip_ksz8081.c | 2 * Copyright 2023-2024 NXP
5 * Copyright (c) 2021 IP-Logix Inc.
8 * SPDX-License-Identifier: Apache-2.0
65 const struct mc_ksz8081_config *config = dev->config; in phy_mc_ksz8081_read()
68 /* Make sure excessive bits 16-31 are reset */ in phy_mc_ksz8081_read()
71 ret = mdio_read(config->mdio_dev, config->addr, reg_addr, (uint16_t *)data); in phy_mc_ksz8081_read()
82 const struct mc_ksz8081_config *config = dev->config; in phy_mc_ksz8081_write()
85 ret = mdio_write(config->mdio_dev, config->addr, reg_addr, (uint16_t)data); in phy_mc_ksz8081_write()
95 const struct mc_ksz8081_config *config = dev->config; in phy_mc_ksz8081_autonegotiate()
104 LOG_ERR("Error reading phy (%d) basic control register", config->addr); in phy_mc_ksz8081_autonegotiate()
[all …]
|
| /Zephyr-latest/include/zephyr/net/ |
| D | phy.h | 8 * Copyright (c) 2021 IP-Logix Inc.
11 * SPDX-License-Identifier: Apache-2.0
31 /** @brief Ethernet link speeds. */
33 /** 10Base-T Half-Duplex */
35 /** 10Base-T Full-Duplex */
37 /** 100Base-T Half-Duplex */
39 /** 100Base-T Full-Duplex */
41 /** 1000Base-T Half-Duplex */
43 /** 1000Base-T Full-Duplex */
45 /** 2.5GBase-T Full-Duplex */
[all …]
|
| D | mii.h | 5 * SPDX-License-Identifier: Apache-2.0
33 /** Auto-Negotiation Advertisement Register */
35 /** Auto-Negotiation Link Partner Ability Reg */
37 /** Auto-Negotiation Expansion Register */
39 /** Auto-Negotiation Next Page Transmit Register */
41 /** Auto-Negotiation Link Partner Received Next Page Reg */
43 /** 1000BASE-T Control Register */
45 /** 1000BASE-T Status Register */
61 /** Auto-Negotiation enable */
67 /** restart auto-negotiation */
[all …]
|
| /Zephyr-latest/dts/bindings/ethernet/ |
| D | nxp,kinetis-ethernet.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,kinetis-ethernet"
8 include: ["ethernet-controller.yaml", "pinctrl-device.yaml"]
15 phy-addr:
19 reset-gpios:
20 type: phandle-array
22 int-gpios:
23 type: phandle-array
27 child-binding:
28 description: Fixed link ethernet node
[all …]
|
| D | xlnx,gem.yaml | 3 # SPDX-License-Identifier: Apache-2.0
10 include: ethernet-controller.yaml
19 clock-frequency:
26 is determined by the current link speed reported by the PHY, to
27 which it will be adjusted at run-time. Therefore, the value of this
29 respective GEM's TX clock - by default, this is the IO PLL.
31 mdc-divider:
42 init-mdio-phy:
45 Activates the management of a PHY associated with the controller in-
46 stance. If this parameter is activated at the board level, the de-
[all …]
|
| /Zephyr-latest/drivers/ethernet/ |
| D | phy_xlnx_gem.c | 6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
[all …]
|
| /Zephyr-latest/boards/bbc/microbit/ |
| D | board.cmake | 1 # SPDX-License-Identifier: Apache-2.0
3 board_runner_args(pyocd "--target=nrf51822")
4 board_runner_args(jlink "--device=nRF51822_xxAA" "--speed=4000")
6 # Note: micro:bit DAPLink may be upgraded to J-Link OB by following the instructions at
7 # https://www.segger.com/products/debug-probes/j-link/models/other-j-links/bbc-microbit-j-link-upgr…
9 set(OPENOCD_NRF5_INTERFACE "cmsis-dap")
14 include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
|
| /Zephyr-latest/boards/bbc/microbit_v2/ |
| D | board.cmake | 1 # SPDX-License-Identifier: Apache-2.0
3 board_runner_args(pyocd "--target=nrf52833")
4 board_runner_args(nrfjprog "--nrf-family=NRF52")
5 board_runner_args(jlink "--device=nRF52833_xxAA" "--speed=4000")
7 # Note: micro:bit v2 DAPLink may be upgraded to J-Link OB by following the instructions at
8 # https://www.segger.com/products/debug-probes/j-link/models/other-j-links/bbc-microbit-j-link-upgr…
10 set(OPENOCD_NRF5_INTERFACE "cmsis-dap")
14 include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake)
|
| /Zephyr-latest/scripts/west_commands/runners/ |
| D | jlink.py | 3 # SPDX-License-Identifier: Apache-2.0
5 '''Runner for debugging with J-Link.'''
47 setattr(args, self.dest, not option.startswith('--no-'))
50 '''Runner front-end for the J-Link GDB server.'''
55 iface='swd', speed='auto', flash_script = None, argument
78 self.speed = speed
81 self.tui_arg = ['-tui'] if tui else []
101 def dev_id_help(cls) -> str:
102 return '''Device identifier. Use it to select the J-Link Serial Number
103 of the device connected over USB. If the J-Link is connected over ip,
[all …]
|
| D | silabs_commander.py | 3 # Based on J-Link runner
5 # SPDX-License-Identifier: Apache-2.0
21 def __init__(self, cfg, device, dev_id, commander, dt_flash, erase, speed, tool_opt): argument
33 self.speed = speed
50 def dev_id_help(cls) -> str:
51 return '''Device identifier. Use it to select the J-Link Serial Number
55 def tool_opt_help(cls) -> str:
56 return "Additional options for Simplicity Commander, e.g. '--noreset'"
61 parser.add_argument('--device', required=True,
65 parser.add_argument('--commander', default=DEFAULT_APP,
[all …]
|
| /Zephyr-latest/dts/bindings/dsa/ |
| D | microchip,ksz8794.yaml | 2 # SPDX-License-Identifier: Apache-2.0
17 0x02: 1) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
18 0x04: 2) CAT-5E/6 Short Cable with a Link Issue for the KSZ8795 Family
19 mii-lowspeed-drivestrength:
22 Define the Low-Speed Interface Drive Strength for MII and RMMI
26 - 2
27 - 4
28 - 8
29 - 12
30 - 16
[all …]
|
| /Zephyr-latest/doc/develop/flash_debug/ |
| D | nordic_segger.rst | 5 Nordic nRF5x Segger J-Link
14 * Segger J-Link firmware and desktop tools
16 * Mass Storage device for drag-and-drop image flashing
21 Segger J-Link Software Installation
24 To install the J-Link Software and documentation pack, follow the steps below:
26 #. Download the appropriate package from the `J-Link Software and documentation pack`_ website
28 #. When connecting a J-Link-enabled board such as an nRF5x DK, PDK or dongle, a
31 nRF5x Command-Line Tools Installation
34 The nRF5x command-line Tools allow you to control your nRF5x device from the command line,
37 To install them, visit `nRF5x Command-Line Tools`_ and select your operating
[all …]
|
| /Zephyr-latest/boards/gd/gd32f470i_eval/ |
| D | board.cmake | 2 # SPDX-License-Identifier: Apache-2.0
4 # GD32F470xx series is not yet supported by SEGGER J-Link
5 board_runner_args(jlink "--device=GD32F450IK" "--speed=4000")
|
| /Zephyr-latest/boards/st/nucleo_h723zg/doc/ |
| D | index.rst | 6 The STM32 Nucleo-144 board provides an affordable and flexible way for users
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK V3 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
27 - 2 user and reset push-buttons
28 - 32.768 kHz crystal oscillator
[all …]
|
| /Zephyr-latest/boards/renesas/ek_ra6m3/doc/ |
| D | index.rst | 9 The Renesas RA6M3 group uses the high-performance Arm® Cortex®-M4 core and
12 embedded RAM, and USB High Speed (HS).
14 The key features of the EK-RA6M3 board are categorized in three groups as follow:
18 - 120MHz Arm Cortex-M4 based RA6M3 MCU in 176 pins, LQFP package
19 - Native pin access through 4 x 40-pin male headers
20 - MCU and USB current measurement points for precision current consumption measurement
21 - Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals,
27 - USB Full Speed Host and Device (micro AB connector)
28 - Four 5V input sources
30 - USB (Debug, Full Speed, High Speed)
[all …]
|
| /Zephyr-latest/doc/hardware/peripherals/ |
| D | w1.rst | 3 1-Wire Bus
9 1-Wire is a low speed half-duplex serial bus using only a single wire plus
11 Similarly to I2C, 1-Wire uses a bidirectional open-collector data line,
14 The 1-Wire bus supports longer bus lines than I2C, while it reaches speeds of up
16 Reliable communication in standard speed configuration is possible with 10 nodes
17 over a bus length of 100 meters. Using overdrive speed, 3 nodes on a bus of
23 .. figure:: 1-Wire_bus_topology.drawio.svg
25 :alt: 1-Wire bus topology
27 A typical 1-Wire bus topology
30 .. _w1-master-api:
[all …]
|
| /Zephyr-latest/boards/st/stm32f769i_disco/doc/ |
| D | index.rst | 7 from audio, multi-sensor support, graphics, security, security, video,
8 and high-speed connectivity features. Important board features include:
10 - STM32F769NIH6 microcontroller featuring 2 Mbytes of Flash memory and 512 Kbytes of RAM, in BGA216…
11 - On-board ST-LINK/V2-1 supporting USB reenumeration capability
12 - USB ST-LINK functions: virtual COM port, mass storage, debug port
13 - Five power supply options:
15 - ST LINK/V2-1
16 - USB HS connector
17 - 5 V from RJ45 (Power Over Ethernet)
18 - 5 V from Arduino™ or external connector
[all …]
|
| /Zephyr-latest/boards/gd/gd32f407v_start/doc/ |
| D | index.rst | 6 The GD32F407V-START board is a hardware platform that enables prototyping
7 on GD32F407VE Cortex-M4 High Performance MCU.
9 The GD32F407VE features a single-core ARM Cortex-M4 MCU which can run up
16 - GD32F407VET6 MCU
17 - 1 x User LEDs
18 - 1 x User Push buttons
19 - 1 x USART
20 - GD-Link on board programmer
21 - J-Link/SWD connector
23 For more information about the GD32F407 SoC and GD32F407V-START board:
[all …]
|
| /Zephyr-latest/boards/st/nucleo_h755zi_q/doc/ |
| D | index.rst | 6 The NUCLEO-H755ZI-Q board, based on the MB1363 reference board, provides an affordable and
13 The NUCLEO-H755ZI-Q board does not require any separate probe as it integrates
14 the ST-LINK V3 debugger/programmer.
18 - STM32H755ZIT6 microcontroller in LQFP144 package
19 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
20 - USB OTG or full-speed device (depending on STM32 support)
21 - 3 user LEDs
22 - 2 user and reset push-buttons
23 - 32.768 kHz crystal oscillator
24 - Board connectors:
[all …]
|
| /Zephyr-latest/dts/arm/xilinx/ |
| D | zynqmp.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-r.dtsi>
9 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
10 #include <zephyr/dt-bindings/ethernet/xlnx_gem.h>
16 compatible = "xlnx,pinctrl-zynqmp";
19 compatible = "soc-nv-flash";
24 compatible = "mmio-sram";
29 compatible = "zephyr,memory-region", "xlnx,zynq-ocm";
31 zephyr,memory-region = "OCM";
40 interrupt-names = "irq_0";
[all …]
|
| /Zephyr-latest/subsys/fs/ |
| D | Kconfig | 3 # SPDX-License-Identifier: Apache-2.0
8 bool "Link file system libraries into build"
10 Link in the underlying file system libraries. This can be
26 module-str = fs
30 bool "Link 'app' with FS"
47 default -1
51 file name length for enabled in-tree file systems. This
52 default may be inappropriate when registering an out-of-tree
88 read/write/erase tests with speed output.
|
| /Zephyr-latest/boards/st/nucleo_f756zg/doc/ |
| D | index.rst | 6 The STM32 Nucleo-144 boards offer combinations of performance and power that
11 The Arduino-compatible ST Zio connector expands functionality of the Nucleo
15 The STM32 Nucleo-144 board does not require any separate probe as it integrates
16 the ST-LINK/V2-1 debugger/programmer.
18 The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
23 - STM32 microcontroller in LQFP144 package
24 - Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
25 - USB OTG or full-speed device (depending on STM32 support)
26 - 3 user LEDs
27 - 2 user and reset push-buttons
[all …]
|
