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/Zephyr-latest/dts/bindings/mipi-dbi/
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [mipi-dbi-device.yaml]
15 Selecting half duplex allows to use SPI MOSI as a bidirectional line,
16 typically used when only one data line is connected.
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
24 SPI clock polarity which indicates the clock idle state.
25 If it is used, the clock idle state is logic high; otherwise, low.
26 mipi-cpha:
31 mipi-hold-cs:
/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
/Zephyr-latest/samples/drivers/led/led_strip/boards/
Desp32c3_devkitm.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/led/led.h>
11 line-idle-low;
14 compatible = "worldsemi,ws2812-spi";
18 spi-max-frequency = <6400000>;
21 chain-length = <1>; /* arbitrary; change at will */
22 spi-cpha;
23 spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */
24 spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */
25 color-mapping = <LED_COLOR_ID_GREEN
[all …]
Desp32s2_saola.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/led/led.h>
11 line-idle-low;
14 compatible = "worldsemi,ws2812-spi";
18 spi-max-frequency = <6400000>;
21 chain-length = <1>; /* arbitrary; change at will */
22 spi-cpha;
23 spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */
24 spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */
25 color-mapping = <LED_COLOR_ID_GREEN
[all …]
Desp32s3_devkitm_procpu.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/led/led.h>
11 line-idle-low;
14 compatible = "worldsemi,ws2812-spi";
18 spi-max-frequency = <6400000>;
21 chain-length = <1>; /* arbitrary; change at will */
22 spi-cpha;
23 spi-one-frame = <0xf0>; /* 11110000: 625 ns high and 625 ns low */
24 spi-zero-frame = <0xc0>; /* 11000000: 312.5 ns high and 937.5 ns low */
25 color-mapping = <LED_COLOR_ID_GREEN
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_nt35510.h4 * SPDX-License-Identifier: Apache-2.0
27 #define NT35510_CMD_RDDSDR 0x0F /* Read display self-diagnostics result */
45 #define NT35510_CMD_TEOFF 0x34 /* Tearing effect line off */
46 #define NT35510_CMD_TEEON 0x35 /* Tearing effect line on */
48 #define NT35510_CMD_IDMOFF 0x38 /* Idle mode off */
49 #define NT35510_CMD_IDMON 0x39 /* Idle mode on */
53 #define NT35510_CMD_STESL 0x44 /* Set tearing effect scan line */
54 #define NT35510_CMD_GSL 0x45 /* Get scan line */
75 #define NT35510_CMD_RDBWLB 0x70 /* Read black/white low bits */
80 #define NT35510_CMD_RDRGLB 0x75 /* Read red/green low bits */
[all …]
/Zephyr-latest/subsys/testsuite/ztest/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
43 value. Please be aware that increasing it for long-running test cases
58 0 Write only file and line for failed assertions
59 1 Write file, line number, function and reason for failed assertions
64 default -2 if !PREEMPT_ENABLED
65 default -1
67 Set priority of the testing thread. Default is -1 (cooperative).
87 bool "Using a pre-defined fatal handler and hook function"
89 Use the pre-defined common fatal error handler and a post hook to
95 bool "Using a pre-defined assert handler and hook function"
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
56 Min. time, in nanoseconds, the #CS line should remain inactive between
[all …]
/Zephyr-latest/boards/espressif/esp32c3_rust/
Desp32c3_rust.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "esp32c3_rust-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/led/led.h>
16 model = "Espressif ESP32C3-RUST";
22 zephyr,shell-uart = &usb_serial;
24 zephyr,code-partition = &slot0_partition;
30 i2c-0 = &i2c0;
32 led-strip = &led_strip;
[all …]
/Zephyr-latest/boards/adafruit/qt_py_esp32s3/
Dadafruit_qt_py_esp32s3_procpu.dts5 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include <zephyr/dt-bindings/led/led.h>
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
13 #include "adafruit_qt_py_esp32s3-pinctrl.dtsi"
19 compatible = "seeed,xiao-esp32s3";
24 zephyr,shell-uart = &usb_serial;
26 zephyr,code-partition = &slot0_partition;
27 zephyr,bt-hci = &esp32_bt_hci;
31 i2c-0 = &i2c0;
[all …]
/Zephyr-latest/boards/m5stack/m5stack_atoms3_lite/
Dm5stack_atoms3_lite_procpu.dts5 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "m5stack_atoms3_lite-pinctrl.dtsi"
11 #include <dt-bindings/led/led.h>
12 #include <dt-bindings/led/worldsemi_ws2812c.h>
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
23 zephyr,shell-uart = &usb_serial;
25 zephyr,code-partition = &slot0_partition;
26 zephyr,bt-hci = &esp32_bt_hci;
32 i2c-0 = &i2c0;
[all …]
/Zephyr-latest/soc/nordic/nrf52/
DKconfig1 # Nordic Semiconductor nRF52 MCU line
3 # Copyright (c) 2016-2023 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
42 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
69 gpio-as-nreset;
73 bool "The instruction cache (I-Cache)"
89 (XO) is used then low frequency clock initially starts with RC and then
111 sometimes wrong. This occurs when the system enters IDLE and stops the
/Zephyr-latest/boards/m5stack/m5stack_atom_lite/
Dm5stack_atom_lite_procpu.dts6 * SPDX-License-Identifier: Apache-2.0
8 /dts-v1/;
11 #include "m5stack_atom_lite-pinctrl.dtsi"
13 #include <zephyr/dt-bindings/input/input-event-codes.h>
14 #include <zephyr/dt-bindings/led/led.h>
15 #include <zephyr/dt-bindings/led/worldsemi_ws2812c.h>
20 compatible = "m5stack,m5stack-atom-lite";
25 zephyr,shell-uart = &uart0;
27 zephyr,code-partition = &slot0_partition;
28 zephyr,bt-hci = &esp32_bt_hci;
[all …]
/Zephyr-latest/boards/m5stack/m5stack_stamps3/
Dm5stack_stamps3_procpu.dts4 * SPDX-License-Identifier: Apache-2.0
6 /dts-v1/;
9 #include "m5stack_stamps3-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/pwm/pwm.h>
12 #include <dt-bindings/led/led.h>
13 #include <dt-bindings/led/worldsemi_ws2812c.h>
14 #include <zephyr/dt-bindings/input/input-event-codes.h>
24 zephyr,shell-uart = &usb_serial;
26 zephyr,code-partition = &slot0_partition;
27 zephyr,bt-hci = &esp32_bt_hci;
[all …]
/Zephyr-latest/drivers/sensor/tsic_xx6/
Dtsic_xx6.c4 * SPDX-License-Identifier: Apache-2.0
68 data->buf_index = FRAME_START_BIT_MSB; in tsic_xx6_buf_reset()
73 return data->buf_index == FRAME_START_BIT_MSB; in tsic_xx6_is_buf_reset()
78 /* If the period is larger than two frames assume the data line has been idle */ in tsic_xx6_is_data_line_idle()
79 return period_cycles > data->frame_cycles * 2; in tsic_xx6_is_data_line_idle()
87 const struct tsic_xx6_config *config = tsic_xx6_dev->config; in tsic_xx6_pwm_callback()
88 struct tsic_xx6_data *data = tsic_xx6_dev->data; in tsic_xx6_pwm_callback()
92 if (dev != config->pwm.dev || channel != config->pwm.channel) { in tsic_xx6_pwm_callback()
102 LOG_ERR("unexpected data idle"); in tsic_xx6_pwm_callback()
107 * Calculate low cycles: The sensor sends the pulse in the last part of the period. The PWM in tsic_xx6_pwm_callback()
[all …]
/Zephyr-latest/drivers/spi/
Dspi_nrfx_spis.c4 * SPDX-License-Identifier: Apache-2.0
65 const struct spi_nrfx_config *dev_config = dev->config; in configure()
66 struct spi_nrfx_data *dev_data = dev->data; in configure()
67 struct spi_context *ctx = &dev_data->ctx; in configure()
74 if (spi_cfg->operation & SPI_HALF_DUPLEX) { in configure()
75 LOG_ERR("Half-duplex not supported"); in configure()
76 return -ENOTSUP; in configure()
79 if (SPI_OP_MODE_GET(spi_cfg->operation) == SPI_OP_MODE_MASTER) { in configure()
80 LOG_ERR("Master mode is not supported on %s", dev->name); in configure()
81 return -EINVAL; in configure()
[all …]
/Zephyr-latest/doc/kernel/services/
Dinterrupts.rst9 allowing the response to occur with very low overhead.
43 in mid-execution if a higher priority interrupt is signaled. The lower
62 Multi-level Interrupt Handling
65 A hardware platform can support more interrupt lines than natively-provided
67 hardware interrupts are combined into one line that is then routed to
75 A unique 32-bit interrupt number is assigned with information
77 Service Routine (ISR). Each interrupt level is given a byte within this 32-bit
81 .. code-block:: none
93 * '-' means interrupt line and is numbered from 0 (right most).
95 to nested controllers and one device 'A' on line 4.
[all …]
/Zephyr-latest/arch/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
6 # SPDX-License-Identifier: Apache-2.0
18 # Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that,
37 # is really only necessary for Cortex-M with ARM MPU!
173 symbols above. See the top-level CMakeLists.txt.
180 module-str = arch
186 This option tells the build system that the target system is big-endian.
187 Little-endian architecture is the default and should leave this option
192 line option for gen_isr_tables.py.
195 # Hidden Kconfig option representing the default little-endian architecture
[all …]
/Zephyr-latest/soc/nordic/nrf53/
DKconfig1 # Nordic Semiconductor nRF53 MCU line
4 # SPDX-License-Identifier: Apache-2.0
46 default y if "$(dt_node_int_prop_int,$(VREGMAIN_PATH),regulator-initial-mode)" = 1
47 default y if "$(dt_node_int_prop_int,$(VREGRADIO_PATH),regulator-initial-mode)" = 1
70 exist its idle state (when the WFI/WFE instruction returns) and it is
83 bool "Pre-tick workaround for nRF5340 anomaly 165"
89 Indicates that the pre-tick workaround for the anomaly 165 that affects
121 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
135 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
188 MCU firmware, so when this option is used with the non-secure version of
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_npcx_controller.c4 * SPDX-License-Identifier: Apache-2.0
15 * support for a two-wire SMBus/I2C synchronous serial interface. The following
21 * +<----------------+<----------------------+
23 * +------+ +------------+ | +------- ----+ | +------- -------+ |
24 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
25 * | +------+ +------------+ +------------+ Yes +---------------+ |
27 * | +-----------+ |
28 * +--------------------------------------------| WAIT_STOP |<------------+
29 * STOP is completed +-----------+ Issue STOP
35 * +<-----------------+<---------------------+
[all …]
/Zephyr-latest/boards/native/native_sim/doc/
Dindex.rst3 Native simulator - native_sim
63 .. zephyr-app-commands::
64 :zephyr-app: samples/hello_world
65 :host-os: unix
77 .. code-block:: console
82 This executable accepts several command line options depending on the
84 You can run it with the ``--help`` command line switch to get a list of
87 .. code-block:: console
89 $ ./build/zephyr/zephyr.exe --help
92 finished. It simply goes into the idle loop forever.
[all …]
/Zephyr-latest/drivers/timer/
Dstm32_lptim_timer.c5 * SPDX-License-Identifier: Apache-2.0
54 * - system clock based on an LPTIM instance, clocked by LSI or LSE
55 * - prescaler is set to a 2^value from 1 (division of the LPTIM source clock by 1)
57 * - using LPTIM AutoReload capability to trig the IRQ (timeout irq)
58 * - when timeout irq occurs the counter is already reset
59 * - the maximum timeout duration is reached with the lptim_time_base value
60 * - with prescaler of 1, the max timeout (LPTIM_TIMEBASE) is 2 seconds:
62 * - with prescaler of 128, the max timeout (LPTIM_TIMEBASE) is 256 seconds:
88 (COND_CODE_1(CONFIG_SMP, (arch_curr_cpu()->id), (_current_cpu->id)))
96 * case because the LPTIM is not clocked in some low power mode state.
[all …]
/Zephyr-latest/include/zephyr/arch/
Darch_interface.h4 * SPDX-License-Identifier: Apache-2.0
8 * @defgroup arch-interface Architecture Interface
13 * call architecture-specific API so will have the prototypes for the
14 * architecture-specific APIs here. Architecture APIs that aren't used in this
17 * The set of architecture-specific APIs used internally by public macros and
53 * @defgroup arch-timing Architecture timing APIs
54 * @ingroup arch-interface
82 * through the full 64 bit space, wrapping at 2^64-1. Hardware with
92 * @addtogroup arch-threads
126 * buffer, defined as the area usable for thread stack context and thread-
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/spi/spi.h>
57 * Clock Polarity: if set, clock idle state will be 1
66 * capture will occur on low to high transition and high to low if
73 * Whatever data is transmitted is looped-back to the receiving buffer of
115 /** Requests - if possible - to keep CS asserted after the transaction */
125 * low. However, some devices may require the reverse logic: active high.
128 * the CS control to a gpio line through struct spi_cs_control would be
143 #define SPI_LINES_SINGLE (0U << 16) /**< Single line */
155 * This can be used to control a CS line via a GPIO line, instead of
[all …]
/Zephyr-latest/include/zephyr/usb_c/
Dtcpci.h3 * SPDX-License-Identifier: Apache-2.0
15 * Registers and fields are compliant to the Type-C Port Controller Interface
19 /** Register address - vendor id */
22 /** Register address - product id */
25 /** Register address - version of TCPC */
28 /** Register address - USB TypeC version */
30 /** Mask for major part of type-c release supported */
32 /** Macro to extract the major part of type-c release supported */
34 /** Mask for minor part of type-c release supported */
36 /** Macro to extract the minor part of type-c release supported */
[all …]

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