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/Zephyr-Core-3.5.0/dts/bindings/serial/
Dns16550.yaml5 include: [uart-controller.yaml, pcie-device.yaml, pinctrl-device.yaml, reset-device.yaml]
8 reg-shift:
21 io-mapped:
23 description: specify registers are IO mapped or memory mapped
/Zephyr-Core-3.5.0/dts/bindings/adc/
Dinfineon,cat1-adc.yaml4 # SPDX-License-Identifier: Apache-2.0
9 manual (Section Port I/O functions) for the group/chanel mapping to a specific port-pin on
10 the board. For example on the cy8cproto_062_4343w P10.0 is mapped to adc0,channel0 and
11 P10.1 is mapped to adc0,channel1.
13 compatible: "infineon,cat1-adc"
15 include: adc-controller.yaml
24 "#io-channel-cells":
27 io-channel-cells:
28 - input
Dinfineon,xmc4xxx-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
7 (Section Port I/O functions) for the group/chanel mapping to a specific port-pin on the board.
8 For example on the xmc45_relax_kit P14.0 is mapped to adc0,channel0 and P14.1 is mapped to
11 compatible: "infineon,xmc4xxx-adc"
13 include: adc-controller.yaml
22 vref-internal-mv:
28 "#io-channel-cells":
31 io-channel-cells:
32 - input
/Zephyr-Core-3.5.0/dts/x86/intel/
Dia32.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
18 d-cache-line-size = <64>;
26 #address-cells = <1>;
27 #interrupt-cells = <3>;
29 interrupt-controller;
35 interrupt-controller;
36 #interrupt-cells = <3>;
[all …]
Draptor_lake.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/pcie/pcie.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "intel,raptor-lake";
20 d-cache-line-size = <64>;
33 #address-cells = <1>;
[all …]
Dalder_lake.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/pcie/pcie.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "intel,alder-lake";
21 d-cache-line-size = <64>;
34 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/arc/synopsys/
Darc_iot.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/i2c/i2c.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
14 #address-cells = <1>;
15 #size-cells = <0>;
24 intc: arcv2-intc {
25 compatible = "snps,arcv2-intc";
26 interrupt-controller;
27 #interrupt-cells = <2>;
31 compatible = "snps,arc-timer";
[all …]
/Zephyr-Core-3.5.0/dts/bindings/espi/
Dmicrochip,xec-espi-host-dev.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-espi-host-dev"
10 on-bus: espi
30 host-io:
37 host-io-addr-mask:
42 alias address is mapped to in the 80h to 83h I/O range.
44 host-mem:
51 emi-mems:
61 "emi-mem-cells":
65 emi-mem-cells:
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/Zephyr-Core-3.5.0/boards/x86/qemu_x86/
Dqemu_x86_lakemont.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
25 uart-0 = &uart0;
31 zephyr,shell-uart = &uart0;
43 io-mapped;
44 clock-frequency = <1843200>;
46 interrupt-parent = <&intc>;
47 current-speed = <115200>;
48 reg-shift = <2>;
56 interrupt-parent = <&intc>;
/Zephyr-Core-3.5.0/samples/subsys/mgmt/updatehub/
Doverlay-ot.conf2 # SPDX -License-Identifier: Apache-2.0
25 # This follows https://openthread.io/guides/border-router guides
26 # It uses the default values from otbr-web page
52 # Mapped Address: 0:0:0:0:0:ffff:808:808
/Zephyr-Core-3.5.0/arch/x86/core/
Defi.c4 * SPDX-License-Identifier: Apache-2.0
27 return efi->acpi_rsdp; in efi_get_acpi_rsdp()
43 * as Zephyr has only mapped memory it uses and IO it knows about. In
47 * plays with the IO-MMU... the posibilities are endless). But
51 * system as-is; we already know it doesn't overlap with the EFI
56 * environment where it would be running on multi-gigabyte systems and
58 * the problem of the red zone -- SysV reserves 128 bytes of
69 * are also caller-save. Technically X/YMM0-5 are caller-save too,
73 * the caller as spill space for the 4 register-passed arguments (this
74 * ABI is so weird...). We also need two call-preserved scratch
[all …]
/Zephyr-Core-3.5.0/subsys/mgmt/updatehub/
DKconfig1 # Copyright (c) 2018-2023 O.S.Systems
2 # SPDX -License-Identifier: Apache-2.0
5 bool"UpdateHub Firmware Over-the-Air support"
22 UpdateHub is an enterprise-grade solution which makes simple to
24 handles all aspects related to sending Firmware Over-the-Air
55 Server (updatehub-ce) as alternative to the
56 updatehub.io enterprise server.
59 string "User address for the updatehub-ce-server"
103 0 - COAP_BLOCK_16
104 1 - COAP_BLOCK_32
[all …]
/Zephyr-Core-3.5.0/include/zephyr/sys/
Ddevice_mmio.h4 * SPDX-License-Identifier: Apache-2.0
6 * Definitions and helper macros for managing driver memory-mapped
10 * including this separately may be needed for arch-level driver code
22 * @defgroup device-mmio Device memory-mapped IO management
27 /* Storing MMIO addresses in RAM is a system-wide decision based on
30 * If we have an MMU enabled, all physical MMIO regions must be mapped into
33 * If we have PCIE enabled, this does mean that non-PCIE drivers may waste
84 * The mapped linear address will have read-write access to supervisor mode.
101 * read-write access. in device_map()
139 * @defgroup device-mmio-single Single MMIO region macros
[all …]
/Zephyr-Core-3.5.0/drivers/serial/
Duart_ns16550.c1 /* ns16550.c - NS16550D serial driver */
6 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
7 * Copyright (c) 2020-2023 Intel Corp.
9 * SPDX-License-Identifier: Apache-2.0
61 /* If any node has property io-mapped set, we need to support IO port
65 * as io-mapped property is considered always exists and present,
67 * resort to the follow helper to see if any okay nodes have io-mapped
146 * RXRDY pin will go inactive when there are no more charac-
151 * reached, the RXRDY pin will go low active. Once it is acti-
156 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
[all …]
/Zephyr-Core-3.5.0/drivers/pcie/host/
Dpcie_ecam.c4 * SPDX-License-Identifier: Apache-2.0
24 * - handle prefetchable regions
47 const struct pcie_ctrl_config *cfg = dev->config; in pcie_ecam_init()
48 struct pcie_ecam_data *data = dev->data; in pcie_ecam_init()
52 * Flags defined in the PCI Bus Binding to IEEE Std 1275-1994 : in pcie_ecam_init()
64 * t is 1 if the address is aliased (for non-relocatable I/O), below 1 MB (for Memory), in pcie_ecam_init()
69 * 10 denotes 32-bit-address Memory Space in pcie_ecam_init()
70 * 11 denotes 64-bit-address Memory Space in pcie_ecam_init()
71 * bbbbbbbb is the 8-bit Bus Number in pcie_ecam_init()
72 * ddddd is the 5-bit Device Number in pcie_ecam_init()
[all …]
/Zephyr-Core-3.5.0/doc/kernel/drivers/
Dindex.rst57 should support an interrupt-based implementation, rather than polling, unless
60 High-level calls accessed through device-specific APIs, such as
73 up for boot-time initialization.
93 split into read-only and runtime-mutable parts. At a high level we have:
95 .. code-block:: C
104 The ``config`` member is for read-only configuration data set at build time. For
105 example, base memory mapped IO addresses, IRQ line numbers, or other fixed
110 per-instance runtime housekeeping. For example, it may contain reference counts,
113 The ``api`` struct maps generic subsystem APIs to the device-specific
114 implementations in the driver. It is typically read-only and populated at
[all …]
/Zephyr-Core-3.5.0/include/zephyr/xen/public/
Dgrant_table.h1 /* SPDX-License-Identifier: MIT */
7 * page-ownership transfers.
40 * device drivers for block and network IO.
50 * This capability-based system allows shared-memory communications
62 /* Some rough guidelines on accessing and updating grant-table entries
63 * in a concurrency-safe manner. For more information, Linux contains a
65 …* http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/xen/grant-table.c;…
67 * NB. WMB is a no-op on current-generation x86 processors. However, a
71 * 1. Write ent->domid.
72 * 2. Write ent->frame:
[all …]
/Zephyr-Core-3.5.0/drivers/flash/
Dflash_npcx_fiu_nor.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
33 /* Mapped address for flash read via direct access */
37 /* Maximum chip erase time-out in ms */
48 /* Specific control operation for Quad-SPI Nor Flash */
74 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_uma_transceive()
75 struct flash_npcx_nor_data *data = dev->data; in flash_npcx_uma_transceive()
79 qspi_npcx_fiu_mutex_lock_configure(config->qspi_bus, &config->qspi_cfg, in flash_npcx_uma_transceive()
80 data->operation); in flash_npcx_uma_transceive()
83 ret = qspi_npcx_fiu_uma_transceive(config->qspi_bus, cfg, flags); in flash_npcx_uma_transceive()
[all …]
/Zephyr-Core-3.5.0/arch/x86/
DKconfig3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
13 # CPU Families - the SoC configuration should select the right one.
64 # Configuration common to both IA32 and Intel64 sub-architectures.
68 bool "Run in 64-bit mode"
166 bool "Compiler-generated SSEx instructions for floating point math"
194 This value normally need to be page-aligned.
234 Selects the use of the memory-mapped PCI Express Extended
236 IO Port registers.
247 Hidden option to signal building for PC-compatible platforms
[all …]
/Zephyr-Core-3.5.0/boards/riscv/tlsr9518adk80d/doc/
Dindex.rst24 The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256
26 stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interface…
35 - RF conducted antenna
36 - 1 MB External Flash memory with reset button
37 - Chip reset button
38 - Mini USB interface
39 - 4-wire JTAG
40 - 4 LEDs, Key matrix up to 4 keys
41 - 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path)
42 - Dual Digital microphone
[all …]
/Zephyr-Core-3.5.0/doc/develop/debug/
Dindex.rst11 This section is a quick hands-on reference to start debugging your
46 .. code-block:: bash
48 qemu -s -S <image>
54 * ``-S`` Do not start CPU at startup; rather, you must type 'c' in the
56 * ``-s`` Shorthand for :literal:`-gdb tcp::1234`: open a GDB server on
65 .. code-block:: console
70 :makevar:`${QEMU_PIPE}` via CMake, typically :file:`qemu-fifo` within the build
71 directory. You may monitor this file during the run with :command:`tail -f
72 qemu-fifo`.
79 .. code-block:: console
[all …]
/Zephyr-Core-3.5.0/boards/arc/emsdp/doc/
Dindex.rst10 for rapid software development on ARC EM processor-based subsystems. It is intended
12 a wide range of ultra-low power embedded applications such as IoT, sensor fusion,
20 (EM SDP) <https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform>`__
35 +-----------+-----+-----+------+------+----------+------+-------+
39 +-----------+-----+-----+------+------+----------+------+-------+
41 +-----------+-----+-----+------+------+----------+------+-------+
43 +-----------+-----+-----+------+------+----------+------+-------+
45 +-----------+-----+-----+------+------+----------+------+-------+
49 +-----------+------------+-------+-----------------------+
52 | SDIO | on-chip | N | SD-card controller |
[all …]
/Zephyr-Core-3.5.0/doc/releases/
Drelease-notes-3.5.rst38 * CVE-2023-3725 `Zephyr project bug tracker GHSA-2g3m-p6c7-8rr3
39 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2g3m-p6c7-8rr3>`_
41 * CVE-2023-4257 `Zephyr project bug tracker GHSA-853q-q69w-gf5j
42 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-853q-q69w-gf5j>`_
44 * CVE-2023-4258 `Zephyr project bug tracker GHSA-m34c-cp63-rwh7
45 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-m34c-cp63-rwh7>`_
47 * CVE-2023-4259 `Zephyr project bug tracker GHSA-gghm-c696-f4j4
48 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gghm-c696-f4j4>`_
50 * CVE-2023-4260 `Zephyr project bug tracker GHSA-gj27-862r-55wh
51 <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gj27-862r-55wh>`_
[all …]
/Zephyr-Core-3.5.0/boards/posix/doc/
Darch_soc.rst22 Zephyr application, eliminating the need for architecture-specific
45 https://BabbleSim.github.io
56 You must have the 32-bit C library installed in your system
57 (in Ubuntu 16.04 install the gcc-multilib package)
67 for Linux (WSL) because WSL does not support native 32-bit binaries.
72 <https://github.com/microsoft/WSL/issues/2468#issuecomment-374904520>`_ it
102 - There can **not** be busy wait loops in the application code that wait for
109 .. code-block:: c
117 .. code-block:: c
123 - Code that depends on its own execution speed will normally not
[all …]
/Zephyr-Core-3.5.0/drivers/smbus/
Dintel_pch_smbus.c7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
29 * * periph_addr - Peripheral address (Slave address mentioned in the Specs)
30 * * command - First byte to send in the SMBus protocol operations except for
77 * configuration option MMIO or IO method will be used.
92 struct pch_data *data = dev->data; in pch_reg_read()
94 return sys_in8(data->sba + reg); in pch_reg_read()
99 struct pch_data *data = dev->data; in pch_reg_write()
101 sys_out8(val, data->sba + reg); in pch_reg_write()
112 const struct device *dev = data->dev; in host_notify_work()
[all …]

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