1/*
2 * Copyright (c) 2021 Intel Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <mem.h>
10
11#ifndef DT_DRAM_BASE
12#define DT_DRAM_BASE		0
13#endif
14#ifndef DT_DRAM_SIZE
15#define DT_DRAM_SIZE		DT_SIZE_K(4096)
16#endif
17
18#include <intel/lakemont.dtsi>
19
20/ {
21	model = "QEMU X86 (Lakemont) emulator";
22	compatible = "qemu,x86_lakemont_emulator";
23
24	aliases {
25		uart-0 = &uart0;
26	};
27
28	chosen {
29		zephyr,sram = &dram0;
30		zephyr,console = &uart0;
31		zephyr,shell-uart = &uart0;
32	};
33
34	dram0: memory@0 {
35		device_type = "memory";
36		reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
37	};
38
39	soc {
40		uart0: uart@3f8 {
41			compatible = "ns16550";
42			reg = <0x000003f8 0x100>;
43			io-mapped;
44			clock-frequency = <1843200>;
45			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
46			interrupt-parent = <&intc>;
47			current-speed = <115200>;
48			reg-shift = <2>;
49			status = "okay";
50		};
51
52		hpet: hpet@fed00000 {
53			compatible = "intel,hpet";
54			reg = <0xfed00000 0x400>;
55			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
56			interrupt-parent = <&intc>;
57
58			status = "okay";
59		};
60	};
61};
62