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12

/Zephyr-latest/dts/bindings/input/
Danalog-axis.yaml2 # SPDX-License-Identifier: Apache-2.0
12 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 compatible = "analog-axis";
16 poll-period-ms = <15>;
17 axis-x {
18 io-channels = <&adc 0>;
19 in-deadzone = <50>;
20 in-min = <100>;
21 in-max = <800>;
26 compatible: "analog-axis"
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Dcirque,pinnacle-common.yaml2 # SPDX-License-Identifier: Apache-2.0
7 data-ready-gpios:
8 type: phandle-array
20 - "1x"
21 - "2x"
22 - "3x"
23 - "4x"
25 data-mode:
29 Data output mode in which position is reported. In the relative mode
33 - "absolute"
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Dfutaba,sbus.yaml2 # SPDX-License-Identifier: Apache-2.0
7 to send out analogue joystick and switches output.
8 SBUS is an single-wire inverted serial protocol so either you need to use
9 the rx-invert feature of your serial driver or use an external signal inverter.
49 include: [base.yaml, uart-device.yaml]
51 child-binding:
53 SBUS Channel to input-event-code binding
62 Valid range: 1 - 16
/Zephyr-latest/dts/bindings/sensor/
Dnxp,lpcmp.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP low-power analog comparator (LPCMP)
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 enable-output-pin:
22 use-unfiltered-output:
25 Decide whether to use the unfiltered output.
27 enable-output-invert:
30 Decide whether to invert the comparator output.
32 hysteresis-level:
35 - 0
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/Zephyr-latest/samples/drivers/led/pwm/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED1 connected to JP71-11
11 * BBLED controller 1 uses GPIO157/LED2 connected to JP71-13
12 * BBLED controller 2 uses GPIO153/LED3 connected to JP71-5
13 * BBLED controller 3 uses GPIO035/PWM8 connected to JP67-19
17 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
18 * 255 full on. BBLED PWM is 8-bit.
19 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
26 compatible = "pwm-leds";
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Dmec15xxevb_assy6853.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pwm/pwm.h>
10 * BBLED controller 0 uses GPIO156/LED0 connected to JP31-13
11 * BBLED controller 1 uses GPIO157/LED1 connected to JP31-15
12 * BBLED controller 2 uses GPIO153/LED2 connected to JP31-17
15 * and implements duty cycle for blink mode as an 8-bit value where 0 is off and
16 * 255 full on. BBLED PWM is 8-bit.
17 * BBLED-PWM driver get cycles API reports 32KHz/256 or 48M/256.
24 compatible = "pwm-leds";
41 microchip,output-func-invert;
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/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
49 pinctrl-0 = <&uart0_default>;
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Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
17 slew-rate = "normal";
18 drive-strength = "normal";
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
40 compatible: "nxp,rt-iocon-pinctrl"
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Dmicrochip,xec-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
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Dmicrochip,mec5-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
22 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
25 - bias-disable: Disable pull-up/down (default behavior, not required).
26 - bias-pull-down: Enable pull-down resistor.
27 - bias-pull-up: Enable pull-up resistor.
28 - drive-push-pull: Output driver is push-pull (default, not required).
29 - drive-open-drain: Output driver is open-drain.
30 - output-high: Set output state high when pin configured.
31 - output-low: Set output state low when pin configured.
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Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
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Dnordic,nrf-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
20 /* You can put this in places like a board-pinctrl.dtsi file in
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
43 state. You would specify the low-power configuration for the same device
52 include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h header file.
55 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
58 - bias-disable: Disable pull-up/down (default behavior, not required).
59 - bias-pull-up: Enable pull-up resistor.
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Dinfineon,xmc4xxx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
24 The pre-defined nodes only set the alternate function of the output pin. The
27 to the inherited property-allowlist list from pincfg-node.yaml).
31 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
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/Zephyr-latest/include/zephyr/drivers/sensor/
Dmcux_lpcmp.h5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Data structure for the NXP MCUX low-power analog comparator (LPCMP)
26 /** LPCMP output. */
34 /** LPCMP output rising event trigger. */
36 /** LPCMP output falling event trigger. */
63 /** LPCMP internal DAC output voltage value. */
73 /** LPCMP window signal invert. */
75 /** LPCMP window signal invert. */
/Zephyr-latest/dts/bindings/pwm/
Dnxp,pca9685.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP PCA9685 16-channel, 12-bit PWM Fm+ I2C-bus LED controller
6 compatible: "nxp,pca9685-pwm"
8 include: [pwm-controller.yaml, i2c-device.yaml, base.yaml]
14 open-drain:
17 The 16 LEDn outputs are configured with an open-drain structure.
20 och-on-ack:
26 invert:
29 Output logic state inverted. Value to use when no external driver
32 "#pwm-cells":
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/Zephyr-latest/tests/drivers/build_all/input/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
17 #io-channel-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
26 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
32 gpio-controller;
34 #gpio-cells = <0x2>;
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/Zephyr-latest/dts/bindings/display/
Dsitronix,st7796s.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [mipi-dbi-spi-device.yaml, display-controller.yaml]
12 type: uint8-array
19 type: uint8-array
26 type: uint8-array
33 type: uint8-array
40 type: uint8-array
47 type: uint8-array
69 type: uint8-array
72 Display output control adjust. Sets display timing controls
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/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_mchp_mec5.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
22 * We initially clear alternate output disable allowing us to set output state
23 * in the control register. Hardware sets output state bit in both control and
24 * parallel output register bits. Alternate output disable only controls which
27 * alternate function is input or bi-directional.
28 * Note 1: hardware allows input and output to be simultaneously enabled.
41 return -EINVAL; in mec5_config_pin()
46 return -EIO; in mec5_config_pin()
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Dpinctrl_mchp_xec.c2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
16 * Microchip XEC: each GPIO pin has two 32-bit control register.
17 * The first 32-bit register contains all pin features except
41 val |= ((drvstr - 1u) << MCHP_GPIO_CTRL2_DRV_STR_POS); in config_drive_slew()
48 regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk); in config_drive_slew()
53 * None, weak pull-up, weak pull-down, or repeater mode (both pulls enabled).
55 * If the no-bias boolean is set then disable internal pulls.
82 * We initially clear alternate output disable allowing us to set output state
83 * in the control register. Hardware sets output state bit in both control and
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dnrf-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 19-23: Reserved.
15 * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
16 * - 17: Clockpin enable.
17 * - 16: Pin inversion mode.
18 * - 15: Pin low power mode.
19 * - 14..11: Pin output drive configuration.
20 * - 10..9: Pin pull configuration.
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/Zephyr-latest/drivers/pwm/
Dpwm_mchp_xec_bbled.c4 * SPDX-License-Identifier: Apache-2.0
51 * Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
52 * where duty_cycle is an 8-bit value 0 to 255.
53 * Prescale is derived from DELAY register LOW_DELAY 12-bit field
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
97 /* Output delay in clocks for initial enable and enable on resume from sleep
140 * DELAY.LO = pre-scaler = [0, 4095]
147 const struct pwm_bbled_xec_config * const cfg = dev->config; in xec_pwmbb_progam_pwm()
148 struct bbled_regs * const regs = cfg->regs; in xec_pwmbb_progam_pwm()
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/Zephyr-latest/include/zephyr/audio/
Ddmic.h7 * SPDX-License-Identifier: Apache-2.0
76 * PDM Input/Output signal configuration
99 /** Bit mask to optionally invert PDM clock */
101 /** Bit mask to optionally invert mic data */
111 * Configuration of the PCM streams to be output by the PDM hardware
128 * Mapping/ordering of the PDM channels to logical PCM output channel
137 * Each channel is described as a 4-bit number, the least significant
141 * - bits 0-3 are for channel 0, bit 0 indicates LEFT or RIGHT
142 * - bits 4-7 are for channel 1, bit 4 indicates LEFT or RIGHT
208 * @return Bit-map containing the PDM and L/R channel information
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/Zephyr-latest/include/zephyr/drivers/
Dgpio.h2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * Copyright (c) 2015-2016 Intel Corporation.
7 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/gpio/gpio.h>
43 * @name GPIO input/output configuration flags
50 /** Enables pin as output, no change to the output state. */
53 /** Disables pin for both input and output. */
58 /* Initializes output to a low state. */
61 /* Initializes output to a high state. */
64 /* Initializes output based on logic level */
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/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.c4 * SPDX-License-Identifier: Apache-2.0
61 -0,
62 -1,
63 -8,
64 -27,
65 -64,
66 -125,
67 -216,
68 -343,
69 -512,
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