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/hal_espressif-latest/components/hal/include/hal/
Di2s_types.h22 * @brief I2S channel slot mode
25 …I2S_SLOT_MODE_MONO = 1, /*!< I2S channel slot format mono, transmit same data in all slot…
26 …I2S_SLOT_MODE_STEREO = 2, /*!< I2S channel slot format stereo, transmit different data in d…
30 * @brief I2S channel direction
33 I2S_DIR_RX_ = BIT(0), /*!< I2S channel direction RX */
34 I2S_DIR_TX_ = BIT(1), /*!< I2S channel direction TX */
38 * @brief I2S controller role
41 …I2S_ROLE_MASTER, /*!< I2S controller master role, bclk and ws signal will be set to…
42 …I2S_ROLE_SLAVE /*!< I2S controller slave role, bclk and ws signal will be set to …
49 I2S_DATA_BIT_WIDTH_8BIT = 8, /*!< I2S channel data bit-width: 8 */
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Di2s_hal.h13 // The HAL layer for I2S.
31 …i2s_data_bit_width_t data_bit_width; /*!< I2S sample data bit width (valid data bits per sa…
32 i2s_slot_bit_width_t slot_bit_width; /*!< I2S slot bit width (total bits per slot) */
63 …uint32_t total_slot; /*!< I2S total number of slots. If it is smaller than …
98 * @brief I2S clock configuration
101 uint32_t sclk; /*!< I2S module clock */
102 uint32_t mclk; /*!< I2S master clock */
103 uint32_t bclk; /*!< I2S bit clock */
104 uint16_t mclk_div; /*!< I2S master clock division */
105 uint16_t bclk_div; /*!< I2S bit clock division*/
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/hal_espressif-latest/components/hal/esp32/include/hal/
Di2s_ll.h13 // The LL layer for ESP32 I2S register operations
27 // Get I2S hardware instance with giving i2s num
52 * @brief I2S clock configuration structure
56 uint16_t integ; // Integer part of I2S module clock divider
57 uint16_t denom; // Denominator part of I2S module clock divider
58 uint16_t numer; // Numerator part of I2S module clock divider
64 * @param hw Peripheral I2S hardware instance address.
75 * @param hw Peripheral I2S hardware instance address.
84 * @brief I2S DMA generate EOF event on data in FIFO popped out
86 * @param hw Peripheral I2S hardware instance address.
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/hal_espressif-latest/components/hal/esp32s2/include/hal/
Di2s_ll.h13 // The LL layer for ESP32-S2 I2S register operations
28 // Get I2S hardware instance with giving i2s num
49 * @brief I2S clock configuration structure
53 uint16_t integ; // Integer part of I2S module clock divider
54 uint16_t denom; // Denominator part of I2S module clock divider
55 uint16_t numer; // Numerator part of I2S module clock divider
61 * @param hw Peripheral I2S hardware instance address.
72 * @param hw Peripheral I2S hardware instance address.
81 * @brief I2S DMA generate EOF event on data in FIFO popped out
83 * @param hw Peripheral I2S hardware instance address.
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/hal_espressif-latest/components/driver/deprecated/driver/
Di2s_types_legacy.h8 * This file is for the backward compatible to the deprecated I2S APIs,
10 * Please refer to "hal/i2s_types.h" for the latest I2S driver types
11 * Note that only one set of I2S APIs is allowed to be used at the same time
25 * @brief I2S bit width per sample.
35 * @brief I2S bit width per chan.
46 * @brief I2S channel.
49 …I2S_CHANNEL_MONO = 1, /*!< I2S channel (mono), one channel activated. In this mode, you on…
50 …I2S_CHANNEL_STEREO = 2, /*!< I2S channel (stereo), two (or more) channels activated. In this…
58 I2S_TDM_ACTIVE_CH0 = (0x1 << 16), /*!< I2S channel 0 activated */
59 I2S_TDM_ACTIVE_CH1 = (0x1 << 17), /*!< I2S channel 1 activated */
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Di2s.h8 * This file is for the backward compatible to the deprecated I2S APIs,
10 … refer to "driver/i2s_std.h", "driver/i2s_pdm.h" and ""driver/i2s_tdm.h"" for the latest I2S driver
11 * Note that only one set of I2S APIs is allowed to be used at the same time
27 #warning "This set of I2S APIs has been deprecated, \
30 you can enable 'Suppress leagcy driver deprecated warning' option under 'I2S Configuration' menu in…
38 * @brief Set I2S pin number
41 * The I2S peripheral output signals can be connected to multiple GPIO pads.
42 * However, the I2S peripheral input signal can only be connected to one GPIO pad.
44 * @param i2s_num I2S port number
46 …* @param pin I2S Pin structure, or NULL to set 2-channel 8-bit internal DAC pin configur…
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Dadc_i2s_legacy.h21 ADC_I2S_DATA_SRC_IO_SIG = 0, /*!< I2S data from GPIO matrix signal */
22 ADC_I2S_DATA_SRC_ADC = 1, /*!< I2S data from ADC */
31 * @brief Set I2S data source
32 * @param src I2S DMA data source, I2S DMA can get data from digital signals or from ADC.
39 * @brief Initialize I2S ADC mode
Ddac.h54 * I2S left channel will be mapped to DAC channel 1
55 * I2S right channel will be mapped to DAC channel 0
100 * @brief Enable DAC output data from I2S
108 * @brief Disable DAC output data from I2S
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Di2s_ll.h7 // The LL layer for I2S register operations
41 * @brief I2S clock configuration structure
45 uint16_t integ; // Integer part of I2S module clock divider
46 uint16_t denom; // Denominator part of I2S module clock divider
47 uint16_t numer; // Numerator part of I2S module clock divider
51 * @brief I2S module general init, enable I2S clock.
53 * @param hw Peripheral I2S hardware instance address.
61 * @brief I2S module disable I2S clock.
63 * @param hw Peripheral I2S hardware instance address.
71 * @brief Enable I2S tx module clock
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/hal_espressif-latest/components/hal/esp32c6/include/hal/
Di2s_ll.h7 // The LL layer for I2S register operations
41 * @brief I2S clock configuration structure
45 uint16_t integ; // Integer part of I2S module clock divider
46 uint16_t denom; // Denominator part of I2S module clock divider
47 uint16_t numer; // Numerator part of I2S module clock divider
51 * @brief I2S module general init, enable I2S clock.
53 * @param hw Peripheral I2S hardware instance address.
62 * @brief I2S module disable I2S clock.
64 * @param hw Peripheral I2S hardware instance address.
73 * @brief Enable I2S tx module clock
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/hal_espressif-latest/components/hal/esp32c3/include/hal/
Di2s_ll.h7 // The LL layer for I2S register operations
40 * @brief I2S clock configuration structure
44 uint16_t integ; // Integer part of I2S module clock divider
45 uint16_t denom; // Denominator part of I2S module clock divider
46 uint16_t numer; // Numerator part of I2S module clock divider
50 * @brief I2S module general init, enable I2S clock.
52 * @param hw Peripheral I2S hardware instance address.
60 * @brief I2S module disable I2S clock.
62 * @param hw Peripheral I2S hardware instance address.
70 * @brief Enable I2S tx module clock
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/hal_espressif-latest/components/hal/esp32h2/include/hal/
Di2s_ll.h7 // The LL layer for I2S register operations
42 * @brief I2S clock configuration structure
46 uint16_t integ; // Integer part of I2S module clock divider
47 uint16_t denom; // Denominator part of I2S module clock divider
48 uint16_t numer; // Numerator part of I2S module clock divider
52 * @brief I2S module general init, enable I2S clock.
54 * @param hw Peripheral I2S hardware instance address.
63 * @brief I2S module disable I2S clock.
65 * @param hw Peripheral I2S hardware instance address.
74 * @brief Enable I2S tx module clock
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/hal_espressif-latest/components/soc/esp32s3/include/soc/
Di2s_struct.h68 …uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high ad…
69 …update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2…
70 … The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is …
71 …uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & …
73 … : 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0…
74 …uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right a…
77 …uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is re…
78 … uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 … uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
94 …of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data …
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Di2s_reg.h134 /*description: 1: Enable I2S PDM Rx mode . 0: Disable..*/
140 /*description: 1: Enable I2S TDM Rx mode . 0: Disable..*/
146 /*description: I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
167 /*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode..*/
173 /*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start
174 is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is
187 /*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (l
194 /*description: 1: The first channel data value is valid in I2S RX mono mode. 0: The second ch
195 annel data value is valid in I2S RX mono mode..*/
201 /*description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. T
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/hal_espressif-latest/components/soc/esp32c3/include/soc/
Di2s_struct.h68 …uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: …
69 …2_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2…
70 … The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is …
71 …uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol…
73 … 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0…
74 …uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignmen…
77 …uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received …
78 uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
79 uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
92 …of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data …
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Di2s_reg.h120 /*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
126 /*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
132 /*description: I2S Rx bit endian. 1:small endian the LSB is received first.
152 /*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
158 /*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop
159 …when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is …
171 /*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law
178 /*description: 1: The first channel data value is valid in I2S RX mono mode.
179 0: The second channel data value is valid in I2S RX mono mode.*/
185 /*description: Set 1 to update I2S RX registers from APB clock domain to I2S
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/hal_espressif-latest/components/soc/esp32c6/include/soc/
Di2s_struct.h15 * I2S interrupt raw register, valid in level.
41 * I2S interrupt status register.
67 * I2S interrupt enable register.
93 * I2S interrupt clear register.
121 * I2S RX configure register
148 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
152 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
157 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
158 * channel data value is valid in I2S RX mono mode.
162 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
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Di2s_reg.h15 * I2S interrupt raw register, valid in level.
48 * I2S interrupt status register.
81 * I2S interrupt enable register.
114 * I2S interrupt clear register.
147 * I2S RX configure register
186 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
193 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
201 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
202 * channel data value is valid in I2S RX mono mode.
209 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
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/hal_espressif-latest/components/soc/esp32h2/include/soc/
Di2s_struct.h15 * I2S interrupt raw register, valid in level.
41 * I2S interrupt status register.
67 * I2S interrupt enable register.
93 * I2S interrupt clear register.
121 * I2S RX configure register
142 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
143 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
151 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
155 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
160 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
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Di2s_reg.h15 * I2S interrupt raw register, valid in level.
48 * I2S interrupt status register.
81 * I2S interrupt enable register.
114 * I2S interrupt clear register.
147 * I2S RX configure register
179 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
180 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
194 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
201 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
209 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
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/hal_espressif-latest/components/driver/include/esp_private/
Di2s_platform.h19 * @brief Hold the I2S port occupation
21 …* @note This private API is used to avoid applications from using the same I2S instance for differ…
24 * @param id I2S port number
25 * @param comp_name The name of compnant that occupied this i2s controller
27 * - ESP_OK: The specific I2S port is free and register the new device object successfully
29 * - ESP_ERR_NOT_FOUND Specific I2S port is not available
34 * @brief Release the I2S port occupation
38 * @param id I2S port number
40 …* - ESP_OK: Deregister I2S port successfully (i.e. that I2S port can used used by other users…
42 * - ESP_ERR_INVALID_STATE: Specific I2S port is free already
/hal_espressif-latest/components/driver/deprecated/
Di2s_legacy.c54 static const char *TAG = "i2s(legacy)";
72 uint32_t sample_rate_hz; /*!< I2S sample rate */
99 * @brief I2S object instance
103 i2s_port_t i2s_num; /*!< I2S port number*/
104 int queue_size; /*!< I2S event queue size*/
105 QueueHandle_t i2s_queue; /*!< I2S queue handler*/
110 gdma_channel_handle_t rx_dma_chan; /*!< I2S rx gDMA channel handle*/
111 gdma_channel_handle_t tx_dma_chan; /*!< I2S tx gDMA channel handle*/
113 intr_handle_t i2s_isr_handle; /*!< I2S Interrupt handle*/
117 bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
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Dadc1_private.h17 * @brief For I2S dma to claim the usage of ADC1.
20 * The I2S module may have to wait for a short time for the current conversion (if exist) to finish.
32 * The ADC1 may have to wait for some time for the I2S read operation to finish.
41 * @brief to let other tasks use the ADC1 when I2S is not work.
/hal_espressif-latest/zephyr/esp32/src/
Dsoc_random.c25 * reference via I2S into the RNG entropy input. in soc_random_enable()
26 * Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) in soc_random_enable()
75 /* Reset some i2s configuration (possibly redundant as we reset entire in soc_random_disable()
76 * I2S peripheral further down). in soc_random_disable()
86 /* Disable i2s clock */ in soc_random_disable()
102 /* Reset i2s peripheral */ in soc_random_disable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32.c32 reference via I2S into the RNG entropy input. in bootloader_random_enable()
34 Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) in bootloader_random_enable()
80 /* Reset some i2s configuration (possibly redundant as we reset entire in bootloader_random_disable()
81 I2S peripheral further down). */ in bootloader_random_disable()
90 /* Disable i2s clock */ in bootloader_random_disable()
109 /* Reset i2s peripheral */ in bootloader_random_disable()

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