Lines Matching full:i2s
15 * I2S interrupt raw register, valid in level.
48 * I2S interrupt status register.
81 * I2S interrupt enable register.
114 * I2S interrupt clear register.
147 * I2S RX configure register
179 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
180 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
194 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
201 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This
209 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second
210 * channel data value is valid in I2S RX mono mode.
217 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
239 * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
261 * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB
269 * 1: Enable I2S TDM Rx mode . 0: Disable.
276 * 1: Enable I2S PDM Rx mode . 0: Disable.
291 * I2S TX configure register
331 * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
332 * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
346 * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
354 * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This
362 * 1: The first channel data value is valid in I2S TX mono mode. 0: The second
363 * channel data value is valid in I2S TX mono mode.
370 * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
400 * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
422 * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is
430 * 1: Enable I2S TDM Tx mode . 0: Disable.
437 * 1: Enable I2S PDM Tx mode . 0: Disable.
451 * I2S transmitter channel mode configuration bits.
467 * I2S RX configure register 1
479 * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all
489 * I2S Rx half sample bits -1.
504 * I2S TX configure register 1
516 * Set the bits to configure the valid data bit length of I2S transmitter channel. 7:
526 * I2S Tx half sample bits -1.
541 * I2S RX clock configure register
545 * Integral I2S clock divider value
552 * I2S Rx module clock enable signal.
559 * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
575 * I2S TX clock configure register
579 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be
589 * I2S Tx module clock enable signal.
596 * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
612 * I2S RX module clock divider configure register
649 * I2S TX module clock divider configure register
686 * I2S TX PCM2PDM configuration register
690 * I2S TX PDM bypass hp filter or not. The option has been removed.
697 * I2S TX PDM OSR2 value
704 * I2S TX PDM prescale for sigmadelta
711 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
718 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
725 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
732 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
739 * I2S TX PDM sigmadelta dither2 value
746 * I2S TX PDM sigmadelta dither value
753 * I2S TX PDM dac mode enable
760 * I2S TX PDM dac 2channel enable
767 * I2S TX PDM Converter enable
775 * I2S TX PCM2PDM configuration register
779 * I2S TX PDM Fp
786 * I2S TX PDM Fs
810 * I2S TX TDM mode control register
814 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
822 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
830 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
838 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
846 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
854 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
862 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
870 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just
878 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
886 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
894 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
902 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
910 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
918 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
926 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
934 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0
942 * The total channel number of I2S TX TDM mode.
950 * I2S TX TDM mode control register
954 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
962 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
970 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
978 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
986 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
994 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1002 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1010 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1018 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1026 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1034 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1042 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1050 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1058 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1066 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1074 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output
1082 * The total channel number of I2S TX TDM mode.
1099 * I2S RX timing control register
1103 * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
1111 * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
1119 * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
1127 * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
1135 * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
1144 * I2S TX timing control register
1148 * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
1156 * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
1164 * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
1172 * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
1180 * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
1188 * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
1197 * I2S HUNG configure register.
1225 * I2S RX data number control register.
1238 * I2S signal data register
1250 * I2S TX status register
1262 * I2S ETM configure register
1266 * I2S ETM send x words event. When sending word number of
1267 * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event.
1274 * I2S ETM receive x words event. When receiving word number of
1275 * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event.
1287 * I2S version control register