1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _SOC_I2S_REG_H_ 7 #define _SOC_I2S_REG_H_ 8 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 #include "soc.h" 14 #define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) 15 /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 16 /*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ 17 #define I2S_TX_HUNG_INT_RAW (BIT(3)) 18 #define I2S_TX_HUNG_INT_RAW_M (BIT(3)) 19 #define I2S_TX_HUNG_INT_RAW_V 0x1 20 #define I2S_TX_HUNG_INT_RAW_S 3 21 /* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 22 /*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ 23 #define I2S_RX_HUNG_INT_RAW (BIT(2)) 24 #define I2S_RX_HUNG_INT_RAW_M (BIT(2)) 25 #define I2S_RX_HUNG_INT_RAW_V 0x1 26 #define I2S_RX_HUNG_INT_RAW_S 2 27 /* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 28 /*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/ 29 #define I2S_TX_DONE_INT_RAW (BIT(1)) 30 #define I2S_TX_DONE_INT_RAW_M (BIT(1)) 31 #define I2S_TX_DONE_INT_RAW_V 0x1 32 #define I2S_TX_DONE_INT_RAW_S 1 33 /* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 34 /*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/ 35 #define I2S_RX_DONE_INT_RAW (BIT(0)) 36 #define I2S_RX_DONE_INT_RAW_M (BIT(0)) 37 #define I2S_RX_DONE_INT_RAW_V 0x1 38 #define I2S_RX_DONE_INT_RAW_S 0 39 40 #define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) 41 /* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 42 /*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ 43 #define I2S_TX_HUNG_INT_ST (BIT(3)) 44 #define I2S_TX_HUNG_INT_ST_M (BIT(3)) 45 #define I2S_TX_HUNG_INT_ST_V 0x1 46 #define I2S_TX_HUNG_INT_ST_S 3 47 /* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 48 /*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ 49 #define I2S_RX_HUNG_INT_ST (BIT(2)) 50 #define I2S_RX_HUNG_INT_ST_M (BIT(2)) 51 #define I2S_RX_HUNG_INT_ST_V 0x1 52 #define I2S_RX_HUNG_INT_ST_S 2 53 /* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 54 /*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/ 55 #define I2S_TX_DONE_INT_ST (BIT(1)) 56 #define I2S_TX_DONE_INT_ST_M (BIT(1)) 57 #define I2S_TX_DONE_INT_ST_V 0x1 58 #define I2S_TX_DONE_INT_ST_S 1 59 /* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 60 /*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/ 61 #define I2S_RX_DONE_INT_ST (BIT(0)) 62 #define I2S_RX_DONE_INT_ST_M (BIT(0)) 63 #define I2S_RX_DONE_INT_ST_V 0x1 64 #define I2S_RX_DONE_INT_ST_S 0 65 66 #define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) 67 /* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 68 /*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ 69 #define I2S_TX_HUNG_INT_ENA (BIT(3)) 70 #define I2S_TX_HUNG_INT_ENA_M (BIT(3)) 71 #define I2S_TX_HUNG_INT_ENA_V 0x1 72 #define I2S_TX_HUNG_INT_ENA_S 3 73 /* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 74 /*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ 75 #define I2S_RX_HUNG_INT_ENA (BIT(2)) 76 #define I2S_RX_HUNG_INT_ENA_M (BIT(2)) 77 #define I2S_RX_HUNG_INT_ENA_V 0x1 78 #define I2S_RX_HUNG_INT_ENA_S 2 79 /* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 80 /*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/ 81 #define I2S_TX_DONE_INT_ENA (BIT(1)) 82 #define I2S_TX_DONE_INT_ENA_M (BIT(1)) 83 #define I2S_TX_DONE_INT_ENA_V 0x1 84 #define I2S_TX_DONE_INT_ENA_S 1 85 /* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 86 /*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/ 87 #define I2S_RX_DONE_INT_ENA (BIT(0)) 88 #define I2S_RX_DONE_INT_ENA_M (BIT(0)) 89 #define I2S_RX_DONE_INT_ENA_V 0x1 90 #define I2S_RX_DONE_INT_ENA_S 0 91 92 #define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) 93 /* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 94 /*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ 95 #define I2S_TX_HUNG_INT_CLR (BIT(3)) 96 #define I2S_TX_HUNG_INT_CLR_M (BIT(3)) 97 #define I2S_TX_HUNG_INT_CLR_V 0x1 98 #define I2S_TX_HUNG_INT_CLR_S 3 99 /* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 100 /*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ 101 #define I2S_RX_HUNG_INT_CLR (BIT(2)) 102 #define I2S_RX_HUNG_INT_CLR_M (BIT(2)) 103 #define I2S_RX_HUNG_INT_CLR_V 0x1 104 #define I2S_RX_HUNG_INT_CLR_S 2 105 /* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 106 /*description: Set this bit to clear the i2s_tx_done_int interrupt*/ 107 #define I2S_TX_DONE_INT_CLR (BIT(1)) 108 #define I2S_TX_DONE_INT_CLR_M (BIT(1)) 109 #define I2S_TX_DONE_INT_CLR_V 0x1 110 #define I2S_TX_DONE_INT_CLR_S 1 111 /* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 112 /*description: Set this bit to clear the i2s_rx_done_int interrupt*/ 113 #define I2S_RX_DONE_INT_CLR (BIT(0)) 114 #define I2S_RX_DONE_INT_CLR_M (BIT(0)) 115 #define I2S_RX_DONE_INT_CLR_V 0x1 116 #define I2S_RX_DONE_INT_CLR_S 0 117 118 #define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) 119 /* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ 120 /*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ 121 #define I2S_RX_PDM_EN (BIT(20)) 122 #define I2S_RX_PDM_EN_M (BIT(20)) 123 #define I2S_RX_PDM_EN_V 0x1 124 #define I2S_RX_PDM_EN_S 20 125 /* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ 126 /*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/ 127 #define I2S_RX_TDM_EN (BIT(19)) 128 #define I2S_RX_TDM_EN_M (BIT(19)) 129 #define I2S_RX_TDM_EN_V 0x1 130 #define I2S_RX_TDM_EN_S 19 131 /* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ 132 /*description: I2S Rx bit endian. 1:small endian the LSB is received first. 133 0:big endian the MSB is received first.*/ 134 #define I2S_RX_BIT_ORDER (BIT(18)) 135 #define I2S_RX_BIT_ORDER_M (BIT(18)) 136 #define I2S_RX_BIT_ORDER_V 0x1 137 #define I2S_RX_BIT_ORDER_S 18 138 /* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ 139 /*description: 0: WS should be 0 when receiving left channel data and WS is 140 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ 141 #define I2S_RX_WS_IDLE_POL (BIT(17)) 142 #define I2S_RX_WS_IDLE_POL_M (BIT(17)) 143 #define I2S_RX_WS_IDLE_POL_V 0x1 144 #define I2S_RX_WS_IDLE_POL_S 17 145 /* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ 146 /*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ 147 #define I2S_RX_24_FILL_EN (BIT(16)) 148 #define I2S_RX_24_FILL_EN_M (BIT(16)) 149 #define I2S_RX_24_FILL_EN_V 0x1 150 #define I2S_RX_24_FILL_EN_S 16 151 /* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */ 152 /*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ 153 #define I2S_RX_LEFT_ALIGN (BIT(15)) 154 #define I2S_RX_LEFT_ALIGN_M (BIT(15)) 155 #define I2S_RX_LEFT_ALIGN_V 0x1 156 #define I2S_RX_LEFT_ALIGN_S 15 157 /* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */ 158 /*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop 159 when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ 160 #define I2S_RX_STOP_MODE 0x00000003 161 #define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V)<<(I2S_RX_STOP_MODE_S)) 162 #define I2S_RX_STOP_MODE_V 0x3 163 #define I2S_RX_STOP_MODE_S 13 164 /* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ 165 /*description: Set this bit to bypass Compress/Decompress module for received data.*/ 166 #define I2S_RX_PCM_BYPASS (BIT(12)) 167 #define I2S_RX_PCM_BYPASS_M (BIT(12)) 168 #define I2S_RX_PCM_BYPASS_V 0x1 169 #define I2S_RX_PCM_BYPASS_S 12 170 /* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */ 171 /*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law 172 decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ 173 #define I2S_RX_PCM_CONF 0x00000003 174 #define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S)) 175 #define I2S_RX_PCM_CONF_V 0x3 176 #define I2S_RX_PCM_CONF_S 10 177 /* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ 178 /*description: 1: The first channel data value is valid in I2S RX mono mode. 179 0: The second channel data value is valid in I2S RX mono mode.*/ 180 #define I2S_RX_MONO_FST_VLD (BIT(9)) 181 #define I2S_RX_MONO_FST_VLD_M (BIT(9)) 182 #define I2S_RX_MONO_FST_VLD_V 0x1 183 #define I2S_RX_MONO_FST_VLD_S 9 184 /* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 185 /*description: Set 1 to update I2S RX registers from APB clock domain to I2S 186 RX clock domain. This bit will be cleared by hardware after update register done.*/ 187 #define I2S_RX_UPDATE (BIT(8)) 188 #define I2S_RX_UPDATE_M (BIT(8)) 189 #define I2S_RX_UPDATE_V 0x1 190 #define I2S_RX_UPDATE_S 8 191 /* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 192 /*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr 193 with low addr value.*/ 194 #define I2S_RX_BIG_ENDIAN (BIT(7)) 195 #define I2S_RX_BIG_ENDIAN_M (BIT(7)) 196 #define I2S_RX_BIG_ENDIAN_V 0x1 197 #define I2S_RX_BIG_ENDIAN_S 7 198 /* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ 199 /*description: Set this bit to enable receiver in mono mode*/ 200 #define I2S_RX_MONO (BIT(5)) 201 #define I2S_RX_MONO_M (BIT(5)) 202 #define I2S_RX_MONO_V 0x1 203 #define I2S_RX_MONO_S 5 204 /* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 205 /*description: Set this bit to enable slave receiver mode*/ 206 #define I2S_RX_SLAVE_MOD (BIT(3)) 207 #define I2S_RX_SLAVE_MOD_M (BIT(3)) 208 #define I2S_RX_SLAVE_MOD_V 0x1 209 #define I2S_RX_SLAVE_MOD_S 3 210 /* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ 211 /*description: Set this bit to start receiving data*/ 212 #define I2S_RX_START (BIT(2)) 213 #define I2S_RX_START_M (BIT(2)) 214 #define I2S_RX_START_V 0x1 215 #define I2S_RX_START_S 2 216 /* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ 217 /*description: Set this bit to reset Rx AFIFO*/ 218 #define I2S_RX_FIFO_RESET (BIT(1)) 219 #define I2S_RX_FIFO_RESET_M (BIT(1)) 220 #define I2S_RX_FIFO_RESET_V 0x1 221 #define I2S_RX_FIFO_RESET_S 1 222 /* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ 223 /*description: Set this bit to reset receiver*/ 224 #define I2S_RX_RESET (BIT(0)) 225 #define I2S_RX_RESET_M (BIT(0)) 226 #define I2S_RX_RESET_V 0x1 227 #define I2S_RX_RESET_S 0 228 229 #define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024) 230 /* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */ 231 /*description: Enable signal loop back mode with transmitter module and receiver 232 module sharing the same WS and BCK signals.*/ 233 #define I2S_SIG_LOOPBACK (BIT(27)) 234 #define I2S_SIG_LOOPBACK_M (BIT(27)) 235 #define I2S_SIG_LOOPBACK_V 0x1 236 #define I2S_SIG_LOOPBACK_S 27 237 /* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ 238 /*description: I2S transmitter channel mode configuration bits.*/ 239 #define I2S_TX_CHAN_MOD 0x00000007 240 #define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S)) 241 #define I2S_TX_CHAN_MOD_V 0x7 242 #define I2S_TX_CHAN_MOD_S 24 243 /* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ 244 /*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/ 245 #define I2S_TX_PDM_EN (BIT(20)) 246 #define I2S_TX_PDM_EN_M (BIT(20)) 247 #define I2S_TX_PDM_EN_V 0x1 248 #define I2S_TX_PDM_EN_S 20 249 /* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ 250 /*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/ 251 #define I2S_TX_TDM_EN (BIT(19)) 252 #define I2S_TX_TDM_EN_M (BIT(19)) 253 #define I2S_TX_TDM_EN_V 0x1 254 #define I2S_TX_TDM_EN_S 19 255 /* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ 256 /*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big 257 endian the MSB is sent first.*/ 258 #define I2S_TX_BIT_ORDER (BIT(18)) 259 #define I2S_TX_BIT_ORDER_M (BIT(18)) 260 #define I2S_TX_BIT_ORDER_V 0x1 261 #define I2S_TX_BIT_ORDER_S 18 262 /* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ 263 /*description: 0: WS should be 0 when sending left channel data and WS is 1in 264 right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ 265 #define I2S_TX_WS_IDLE_POL (BIT(17)) 266 #define I2S_TX_WS_IDLE_POL_M (BIT(17)) 267 #define I2S_TX_WS_IDLE_POL_V 0x1 268 #define I2S_TX_WS_IDLE_POL_S 17 269 /* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ 270 /*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ 271 #define I2S_TX_24_FILL_EN (BIT(16)) 272 #define I2S_TX_24_FILL_EN_M (BIT(16)) 273 #define I2S_TX_24_FILL_EN_V 0x1 274 #define I2S_TX_24_FILL_EN_S 16 275 /* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */ 276 /*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ 277 #define I2S_TX_LEFT_ALIGN (BIT(15)) 278 #define I2S_TX_LEFT_ALIGN_M (BIT(15)) 279 #define I2S_TX_LEFT_ALIGN_V 0x1 280 #define I2S_TX_LEFT_ALIGN_S 15 281 /* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ 282 /*description: Set this bit to stop disable output BCK signal and WS signal 283 when tx FIFO is emtpy*/ 284 #define I2S_TX_STOP_EN (BIT(13)) 285 #define I2S_TX_STOP_EN_M (BIT(13)) 286 #define I2S_TX_STOP_EN_V 0x1 287 #define I2S_TX_STOP_EN_S 13 288 /* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ 289 /*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ 290 #define I2S_TX_PCM_BYPASS (BIT(12)) 291 #define I2S_TX_PCM_BYPASS_M (BIT(12)) 292 #define I2S_TX_PCM_BYPASS_V 0x1 293 #define I2S_TX_PCM_BYPASS_S 12 294 /* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ 295 /*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law 296 decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ 297 #define I2S_TX_PCM_CONF 0x00000003 298 #define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S)) 299 #define I2S_TX_PCM_CONF_V 0x3 300 #define I2S_TX_PCM_CONF_S 10 301 /* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ 302 /*description: 1: The first channel data value is valid in I2S TX mono mode. 303 0: The second channel data value is valid in I2S TX mono mode.*/ 304 #define I2S_TX_MONO_FST_VLD (BIT(9)) 305 #define I2S_TX_MONO_FST_VLD_M (BIT(9)) 306 #define I2S_TX_MONO_FST_VLD_V 0x1 307 #define I2S_TX_MONO_FST_VLD_S 9 308 /* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ 309 /*description: Set 1 to update I2S TX registers from APB clock domain to I2S 310 TX clock domain. This bit will be cleared by hardware after update register done.*/ 311 #define I2S_TX_UPDATE (BIT(8)) 312 #define I2S_TX_UPDATE_M (BIT(8)) 313 #define I2S_TX_UPDATE_V 0x1 314 #define I2S_TX_UPDATE_S 8 315 /* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ 316 /*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr 317 with low addr value.*/ 318 #define I2S_TX_BIG_ENDIAN (BIT(7)) 319 #define I2S_TX_BIG_ENDIAN_M (BIT(7)) 320 #define I2S_TX_BIG_ENDIAN_V 0x1 321 #define I2S_TX_BIG_ENDIAN_S 7 322 /* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */ 323 /*description: 1: The value of Left channel data is equal to the value of right 324 channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ 325 #define I2S_TX_CHAN_EQUAL (BIT(6)) 326 #define I2S_TX_CHAN_EQUAL_M (BIT(6)) 327 #define I2S_TX_CHAN_EQUAL_V 0x1 328 #define I2S_TX_CHAN_EQUAL_S 6 329 /* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ 330 /*description: Set this bit to enable transmitter in mono mode*/ 331 #define I2S_TX_MONO (BIT(5)) 332 #define I2S_TX_MONO_M (BIT(5)) 333 #define I2S_TX_MONO_V 0x1 334 #define I2S_TX_MONO_S 5 335 /* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ 336 /*description: Set this bit to enable slave transmitter mode*/ 337 #define I2S_TX_SLAVE_MOD (BIT(3)) 338 #define I2S_TX_SLAVE_MOD_M (BIT(3)) 339 #define I2S_TX_SLAVE_MOD_V 0x1 340 #define I2S_TX_SLAVE_MOD_S 3 341 /* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ 342 /*description: Set this bit to start transmitting data*/ 343 #define I2S_TX_START (BIT(2)) 344 #define I2S_TX_START_M (BIT(2)) 345 #define I2S_TX_START_V 0x1 346 #define I2S_TX_START_S 2 347 /* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ 348 /*description: Set this bit to reset Tx AFIFO*/ 349 #define I2S_TX_FIFO_RESET (BIT(1)) 350 #define I2S_TX_FIFO_RESET_M (BIT(1)) 351 #define I2S_TX_FIFO_RESET_V 0x1 352 #define I2S_TX_FIFO_RESET_S 1 353 /* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ 354 /*description: Set this bit to reset transmitter*/ 355 #define I2S_TX_RESET (BIT(0)) 356 #define I2S_TX_RESET_M (BIT(0)) 357 #define I2S_TX_RESET_V 0x1 358 #define I2S_TX_RESET_S 0 359 360 #define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028) 361 /* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ 362 /*description: Set this bit to enable receiver in Phillips standard mode*/ 363 #define I2S_RX_MSB_SHIFT (BIT(29)) 364 #define I2S_RX_MSB_SHIFT_M (BIT(29)) 365 #define I2S_RX_MSB_SHIFT_V 0x1 366 #define I2S_RX_MSB_SHIFT_S 29 367 /* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ 368 /*description: The Rx bit number for each channel minus 1in TDM mode.*/ 369 #define I2S_RX_TDM_CHAN_BITS 0x0000001F 370 #define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V)<<(I2S_RX_TDM_CHAN_BITS_S)) 371 #define I2S_RX_TDM_CHAN_BITS_V 0x1F 372 #define I2S_RX_TDM_CHAN_BITS_S 24 373 /* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ 374 /*description: I2S Rx half sample bits -1.*/ 375 #define I2S_RX_HALF_SAMPLE_BITS 0x0000003F 376 #define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V)<<(I2S_RX_HALF_SAMPLE_BITS_S)) 377 #define I2S_RX_HALF_SAMPLE_BITS_V 0x3F 378 #define I2S_RX_HALF_SAMPLE_BITS_S 18 379 /* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ 380 /*description: Set the bits to configure bit length of I2S receiver channel.*/ 381 #define I2S_RX_BITS_MOD 0x0000001F 382 #define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S)) 383 #define I2S_RX_BITS_MOD_V 0x1F 384 #define I2S_RX_BITS_MOD_S 13 385 /* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ 386 /*description: Bit clock configuration bits in receiver mode.*/ 387 #define I2S_RX_BCK_DIV_NUM 0x0000003F 388 #define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S)) 389 #define I2S_RX_BCK_DIV_NUM_V 0x3F 390 #define I2S_RX_BCK_DIV_NUM_S 7 391 /* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ 392 /*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ 393 #define I2S_RX_TDM_WS_WIDTH 0x0000007F 394 #define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V)<<(I2S_RX_TDM_WS_WIDTH_S)) 395 #define I2S_RX_TDM_WS_WIDTH_V 0x7F 396 #define I2S_RX_TDM_WS_WIDTH_S 0 397 398 #define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C) 399 /* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ 400 /*description: Set this bit to enable transmitter in Phillips standard mode*/ 401 #define I2S_TX_MSB_SHIFT (BIT(29)) 402 #define I2S_TX_MSB_SHIFT_M (BIT(29)) 403 #define I2S_TX_MSB_SHIFT_V 0x1 404 #define I2S_TX_MSB_SHIFT_S 29 405 /* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ 406 /*description: The Tx bit number for each channel minus 1in TDM mode.*/ 407 #define I2S_TX_TDM_CHAN_BITS 0x0000001F 408 #define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V)<<(I2S_TX_TDM_CHAN_BITS_S)) 409 #define I2S_TX_TDM_CHAN_BITS_V 0x1F 410 #define I2S_TX_TDM_CHAN_BITS_S 24 411 /* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ 412 /*description: I2S Tx half sample bits -1.*/ 413 #define I2S_TX_HALF_SAMPLE_BITS 0x0000003F 414 #define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V)<<(I2S_TX_HALF_SAMPLE_BITS_S)) 415 #define I2S_TX_HALF_SAMPLE_BITS_V 0x3F 416 #define I2S_TX_HALF_SAMPLE_BITS_S 18 417 /* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ 418 /*description: Set the bits to configure bit length of I2S transmitter channel.*/ 419 #define I2S_TX_BITS_MOD 0x0000001F 420 #define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S)) 421 #define I2S_TX_BITS_MOD_V 0x1F 422 #define I2S_TX_BITS_MOD_S 13 423 /* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ 424 /*description: Bit clock configuration bits in transmitter mode.*/ 425 #define I2S_TX_BCK_DIV_NUM 0x0000003F 426 #define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S)) 427 #define I2S_TX_BCK_DIV_NUM_V 0x3F 428 #define I2S_TX_BCK_DIV_NUM_S 7 429 /* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ 430 /*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ 431 #define I2S_TX_TDM_WS_WIDTH 0x0000007F 432 #define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V)<<(I2S_TX_TDM_WS_WIDTH_S)) 433 #define I2S_TX_TDM_WS_WIDTH_V 0x7F 434 #define I2S_TX_TDM_WS_WIDTH_S 0 435 436 #define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030) 437 /* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ 438 /*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module 439 clock as I2S_MCLK_OUT.*/ 440 #define I2S_MCLK_SEL (BIT(29)) 441 #define I2S_MCLK_SEL_M (BIT(29)) 442 #define I2S_MCLK_SEL_V 0x1 443 #define I2S_MCLK_SEL_S 29 444 /* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ 445 /*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 446 3: I2S_MCLK_in.*/ 447 #define I2S_RX_CLK_SEL 0x00000003 448 #define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V)<<(I2S_RX_CLK_SEL_S)) 449 #define I2S_RX_CLK_SEL_V 0x3 450 #define I2S_RX_CLK_SEL_S 27 451 /* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 452 /*description: I2S Rx module clock enable signal.*/ 453 #define I2S_RX_CLK_ACTIVE (BIT(26)) 454 #define I2S_RX_CLK_ACTIVE_M (BIT(26)) 455 #define I2S_RX_CLK_ACTIVE_V 0x1 456 #define I2S_RX_CLK_ACTIVE_S 26 457 /* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 458 /*description: Integral I2S clock divider value*/ 459 #define I2S_RX_CLKM_DIV_NUM 0x000000FF 460 #define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V)<<(I2S_RX_CLKM_DIV_NUM_S)) 461 #define I2S_RX_CLKM_DIV_NUM_V 0xFF 462 #define I2S_RX_CLKM_DIV_NUM_S 0 463 464 #define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034) 465 /* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ 466 /*description: Set this bit to enable clk gate*/ 467 #define I2S_CLK_EN (BIT(29)) 468 #define I2S_CLK_EN_M (BIT(29)) 469 #define I2S_CLK_EN_V 0x1 470 #define I2S_CLK_EN_S 29 471 /* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ 472 /*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: 473 CLK160. 3: I2S_MCLK_in.*/ 474 #define I2S_TX_CLK_SEL 0x00000003 475 #define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V)<<(I2S_TX_CLK_SEL_S)) 476 #define I2S_TX_CLK_SEL_V 0x3 477 #define I2S_TX_CLK_SEL_S 27 478 /* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ 479 /*description: I2S Tx module clock enable signal.*/ 480 #define I2S_TX_CLK_ACTIVE (BIT(26)) 481 #define I2S_TX_CLK_ACTIVE_M (BIT(26)) 482 #define I2S_TX_CLK_ACTIVE_V 0x1 483 #define I2S_TX_CLK_ACTIVE_S 26 484 /* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ 485 /*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). 486 There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ 487 #define I2S_TX_CLKM_DIV_NUM 0x000000FF 488 #define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V)<<(I2S_TX_CLKM_DIV_NUM_S)) 489 #define I2S_TX_CLKM_DIV_NUM_V 0xFF 490 #define I2S_TX_CLKM_DIV_NUM_S 0 491 492 #define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038) 493 /* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ 494 /*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > 495 a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ 496 #define I2S_RX_CLKM_DIV_YN1 (BIT(27)) 497 #define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) 498 #define I2S_RX_CLKM_DIV_YN1_V 0x1 499 #define I2S_RX_CLKM_DIV_YN1_S 27 500 /* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ 501 /*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For 502 b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ 503 #define I2S_RX_CLKM_DIV_X 0x000001FF 504 #define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V)<<(I2S_RX_CLKM_DIV_X_S)) 505 #define I2S_RX_CLKM_DIV_X_V 0x1FF 506 #define I2S_RX_CLKM_DIV_X_S 18 507 /* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ 508 /*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b 509 > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ 510 #define I2S_RX_CLKM_DIV_Y 0x000001FF 511 #define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V)<<(I2S_RX_CLKM_DIV_Y_S)) 512 #define I2S_RX_CLKM_DIV_Y_V 0x1FF 513 #define I2S_RX_CLKM_DIV_Y_S 9 514 /* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ 515 /*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 516 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ 517 #define I2S_RX_CLKM_DIV_Z 0x000001FF 518 #define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V)<<(I2S_RX_CLKM_DIV_Z_S)) 519 #define I2S_RX_CLKM_DIV_Z_V 0x1FF 520 #define I2S_RX_CLKM_DIV_Z_S 0 521 522 #define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C) 523 /* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ 524 /*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > 525 a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ 526 #define I2S_TX_CLKM_DIV_YN1 (BIT(27)) 527 #define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) 528 #define I2S_TX_CLKM_DIV_YN1_V 0x1 529 #define I2S_TX_CLKM_DIV_YN1_S 27 530 /* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ 531 /*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For 532 b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ 533 #define I2S_TX_CLKM_DIV_X 0x000001FF 534 #define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V)<<(I2S_TX_CLKM_DIV_X_S)) 535 #define I2S_TX_CLKM_DIV_X_V 0x1FF 536 #define I2S_TX_CLKM_DIV_X_S 18 537 /* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ 538 /*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b 539 > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ 540 #define I2S_TX_CLKM_DIV_Y 0x000001FF 541 #define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V)<<(I2S_TX_CLKM_DIV_Y_S)) 542 #define I2S_TX_CLKM_DIV_Y_V 0x1FF 543 #define I2S_TX_CLKM_DIV_Y_S 9 544 /* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ 545 /*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 546 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ 547 #define I2S_TX_CLKM_DIV_Z 0x000001FF 548 #define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V)<<(I2S_TX_CLKM_DIV_Z_S)) 549 #define I2S_TX_CLKM_DIV_Z_V 0x1FF 550 #define I2S_TX_CLKM_DIV_Z_S 0 551 552 #define I2S_TX_PCM2PDM_CONF_REG(i) (REG_I2S_BASE(i) + 0x040) 553 /* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ 554 /*description: I2S TX PDM Converter enable.*/ 555 #define I2S_PCM2PDM_CONV_EN (BIT(25)) 556 #define I2S_PCM2PDM_CONV_EN_M (BIT(25)) 557 #define I2S_PCM2PDM_CONV_EN_V 0x1 558 #define I2S_PCM2PDM_CONV_EN_S 25 559 /* I2S_TX_PDM_DAC_MODE_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ 560 /*description: I2S TX PDM dac 2channel enable.*/ 561 #define I2S_TX_PDM_DAC_MODE_EN (BIT(24)) 562 #define I2S_TX_PDM_DAC_MODE_EN_M (BIT(24)) 563 #define I2S_TX_PDM_DAC_MODE_EN_V 0x1 564 #define I2S_TX_PDM_DAC_MODE_EN_S 24 565 /* I2S_TX_PDM_DAC_2OUT_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ 566 /*description: I2S TX PDM dac mode enable.*/ 567 #define I2S_TX_PDM_DAC_2OUT_EN (BIT(23)) 568 #define I2S_TX_PDM_DAC_2OUT_EN_M (BIT(23)) 569 #define I2S_TX_PDM_DAC_2OUT_EN_V 0x1 570 #define I2S_TX_PDM_DAC_2OUT_EN_S 23 571 /* I2S_TX_PDM_SIGMADELTA_DITHER : R/W ;bitpos:[22] ;default: 1'b1 ; */ 572 /*description: I2S TX PDM sigmadelta dither value.*/ 573 #define I2S_TX_PDM_SIGMADELTA_DITHER (BIT(22)) 574 #define I2S_TX_PDM_SIGMADELTA_DITHER_M (BIT(22)) 575 #define I2S_TX_PDM_SIGMADELTA_DITHER_V 0x1 576 #define I2S_TX_PDM_SIGMADELTA_DITHER_S 22 577 /* I2S_TX_PDM_SIGMADELTA_DITHER2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ 578 /*description: I2S TX PDM sigmadelta dither2 value.*/ 579 #define I2S_TX_PDM_SIGMADELTA_DITHER2 (BIT(21)) 580 #define I2S_TX_PDM_SIGMADELTA_DITHER2_M (BIT(21)) 581 #define I2S_TX_PDM_SIGMADELTA_DITHER2_V 0x1 582 #define I2S_TX_PDM_SIGMADELTA_DITHER2_S 21 583 /* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[20:19] ;default: 2'h1 ; */ 584 /*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ 585 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT 0x00000003 586 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S)) 587 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V 0x3 588 #define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S 19 589 /* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[18:17] ;default: 2'h1 ; */ 590 /*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ 591 #define I2S_TX_PDM_SINC_IN_SHIFT 0x00000003 592 #define I2S_TX_PDM_SINC_IN_SHIFT_M ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S)) 593 #define I2S_TX_PDM_SINC_IN_SHIFT_V 0x3 594 #define I2S_TX_PDM_SINC_IN_SHIFT_S 17 595 /* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[16:15] ;default: 2'h1 ; */ 596 /*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ 597 #define I2S_TX_PDM_LP_IN_SHIFT 0x00000003 598 #define I2S_TX_PDM_LP_IN_SHIFT_M ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S)) 599 #define I2S_TX_PDM_LP_IN_SHIFT_V 0x3 600 #define I2S_TX_PDM_LP_IN_SHIFT_S 15 601 /* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ 602 /*description: I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4.*/ 603 #define I2S_TX_PDM_HP_IN_SHIFT 0x00000003 604 #define I2S_TX_PDM_HP_IN_SHIFT_M ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S)) 605 #define I2S_TX_PDM_HP_IN_SHIFT_V 0x3 606 #define I2S_TX_PDM_HP_IN_SHIFT_S 13 607 /* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[12:5] ;default: 8'h0 ; */ 608 /*description: I2S TX PDM prescale for sigmadelta.*/ 609 #define I2S_TX_PDM_PRESCALE 0x000000FF 610 #define I2S_TX_PDM_PRESCALE_M ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S)) 611 #define I2S_TX_PDM_PRESCALE_V 0xFF 612 #define I2S_TX_PDM_PRESCALE_S 5 613 /* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[4:1] ;default: 4'h2 ; */ 614 /*description: I2S TX PDM OSR2 value.*/ 615 #define I2S_TX_PDM_SINC_OSR2 0x0000000F 616 #define I2S_TX_PDM_SINC_OSR2_M ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S)) 617 #define I2S_TX_PDM_SINC_OSR2_V 0xF 618 #define I2S_TX_PDM_SINC_OSR2_S 1 619 /* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 620 /*description: I2S TX PDM bypass hp filter or not. The option has been removed..*/ 621 #define I2S_TX_PDM_HP_BYPASS (BIT(0)) 622 #define I2S_TX_PDM_HP_BYPASS_M (BIT(0)) 623 #define I2S_TX_PDM_HP_BYPASS_V 0x1 624 #define I2S_TX_PDM_HP_BYPASS_S 0 625 626 #define I2S_TX_PCM2PDM_CONF1_REG(i) (REG_I2S_BASE(i) + 0x44) 627 /* I2S_TX_IIR_HP_MULT12_0 : R/W ;bitpos:[25:23] ;default: 3'd7 ; */ 628 /*description: The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MUL 629 T12_0[2:0]).*/ 630 #define I2S_TX_IIR_HP_MULT12_0 0x00000007 631 #define I2S_TX_IIR_HP_MULT12_0_M ((I2S_TX_IIR_HP_MULT12_0_V)<<(I2S_TX_IIR_HP_MULT12_0_S)) 632 #define I2S_TX_IIR_HP_MULT12_0_V 0x7 633 #define I2S_TX_IIR_HP_MULT12_0_S 23 634 /* I2S_TX_IIR_HP_MULT12_5 : R/W ;bitpos:[22:20] ;default: 3'd7 ; */ 635 /*description: The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MUL 636 T12_5[2:0]).*/ 637 #define I2S_TX_IIR_HP_MULT12_5 0x00000007 638 #define I2S_TX_IIR_HP_MULT12_5_M ((I2S_TX_IIR_HP_MULT12_5_V)<<(I2S_TX_IIR_HP_MULT12_5_S)) 639 #define I2S_TX_IIR_HP_MULT12_5_V 0x7 640 #define I2S_TX_IIR_HP_MULT12_5_S 20 641 /* I2S_TX_PDM_FS : R/W ;bitpos:[19:10] ;default: 10'd480 ; */ 642 /*description: I2S TX PDM Fs.*/ 643 #define I2S_TX_PDM_FS 0x000003FF 644 #define I2S_TX_PDM_FS_M ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S)) 645 #define I2S_TX_PDM_FS_V 0x3FF 646 #define I2S_TX_PDM_FS_S 10 647 /* I2S_TX_PDM_FP : R/W ;bitpos:[9:0] ;default: 10'd960 ; */ 648 /*description: I2S TX PDM Fp.*/ 649 #define I2S_TX_PDM_FP 0x000003FF 650 #define I2S_TX_PDM_FP_M ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S)) 651 #define I2S_TX_PDM_FP_V 0x3FF 652 #define I2S_TX_PDM_FP_S 0 653 654 #define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x050) 655 /* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ 656 /*description: The total channel number of I2S TX TDM mode.*/ 657 #define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F 658 #define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V)<<(I2S_RX_TDM_TOT_CHAN_NUM_S)) 659 #define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF 660 #define I2S_RX_TDM_TOT_CHAN_NUM_S 16 661 /* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ 662 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 663 Disable just input 0 in this channel.*/ 664 #define I2S_RX_TDM_CHAN15_EN (BIT(15)) 665 #define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) 666 #define I2S_RX_TDM_CHAN15_EN_V 0x1 667 #define I2S_RX_TDM_CHAN15_EN_S 15 668 /* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ 669 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 670 Disable just input 0 in this channel.*/ 671 #define I2S_RX_TDM_CHAN14_EN (BIT(14)) 672 #define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) 673 #define I2S_RX_TDM_CHAN14_EN_V 0x1 674 #define I2S_RX_TDM_CHAN14_EN_S 14 675 /* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ 676 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 677 Disable just input 0 in this channel.*/ 678 #define I2S_RX_TDM_CHAN13_EN (BIT(13)) 679 #define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) 680 #define I2S_RX_TDM_CHAN13_EN_V 0x1 681 #define I2S_RX_TDM_CHAN13_EN_S 13 682 /* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 683 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 684 Disable just input 0 in this channel.*/ 685 #define I2S_RX_TDM_CHAN12_EN (BIT(12)) 686 #define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) 687 #define I2S_RX_TDM_CHAN12_EN_V 0x1 688 #define I2S_RX_TDM_CHAN12_EN_S 12 689 /* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ 690 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 691 Disable just input 0 in this channel.*/ 692 #define I2S_RX_TDM_CHAN11_EN (BIT(11)) 693 #define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) 694 #define I2S_RX_TDM_CHAN11_EN_V 0x1 695 #define I2S_RX_TDM_CHAN11_EN_S 11 696 /* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ 697 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 698 Disable just input 0 in this channel.*/ 699 #define I2S_RX_TDM_CHAN10_EN (BIT(10)) 700 #define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) 701 #define I2S_RX_TDM_CHAN10_EN_V 0x1 702 #define I2S_RX_TDM_CHAN10_EN_S 10 703 /* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ 704 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 705 Disable just input 0 in this channel.*/ 706 #define I2S_RX_TDM_CHAN9_EN (BIT(9)) 707 #define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) 708 #define I2S_RX_TDM_CHAN9_EN_V 0x1 709 #define I2S_RX_TDM_CHAN9_EN_S 9 710 /* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ 711 /*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: 712 Disable just input 0 in this channel.*/ 713 #define I2S_RX_TDM_CHAN8_EN (BIT(8)) 714 #define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) 715 #define I2S_RX_TDM_CHAN8_EN_V 0x1 716 #define I2S_RX_TDM_CHAN8_EN_S 8 717 /* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ 718 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 719 0: Disable just input 0 in this channel.*/ 720 #define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) 721 #define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) 722 #define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 723 #define I2S_RX_TDM_PDM_CHAN7_EN_S 7 724 /* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ 725 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 726 0: Disable just input 0 in this channel.*/ 727 #define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) 728 #define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) 729 #define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 730 #define I2S_RX_TDM_PDM_CHAN6_EN_S 6 731 /* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ 732 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 733 0: Disable just input 0 in this channel.*/ 734 #define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) 735 #define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) 736 #define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 737 #define I2S_RX_TDM_PDM_CHAN5_EN_S 5 738 /* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ 739 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 740 0: Disable just input 0 in this channel.*/ 741 #define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) 742 #define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) 743 #define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 744 #define I2S_RX_TDM_PDM_CHAN4_EN_S 4 745 /* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ 746 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 747 0: Disable just input 0 in this channel.*/ 748 #define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) 749 #define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) 750 #define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 751 #define I2S_RX_TDM_PDM_CHAN3_EN_S 3 752 /* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ 753 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 754 0: Disable just input 0 in this channel.*/ 755 #define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) 756 #define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) 757 #define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 758 #define I2S_RX_TDM_PDM_CHAN2_EN_S 2 759 /* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ 760 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 761 0: Disable just input 0 in this channel.*/ 762 #define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) 763 #define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) 764 #define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 765 #define I2S_RX_TDM_PDM_CHAN1_EN_S 1 766 /* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ 767 /*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 768 0: Disable just input 0 in this channel.*/ 769 #define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) 770 #define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) 771 #define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 772 #define I2S_RX_TDM_PDM_CHAN0_EN_S 0 773 774 #define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054) 775 /* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ 776 /*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM 777 + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ 778 #define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) 779 #define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) 780 #define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 781 #define I2S_TX_TDM_SKIP_MSK_EN_S 20 782 /* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ 783 /*description: The total channel number minus 1 of I2S TX TDM mode.*/ 784 #define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F 785 #define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V)<<(I2S_TX_TDM_TOT_CHAN_NUM_S)) 786 #define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF 787 #define I2S_TX_TDM_TOT_CHAN_NUM_S 16 788 /* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ 789 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 790 Disable just output 0 in this channel.*/ 791 #define I2S_TX_TDM_CHAN15_EN (BIT(15)) 792 #define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) 793 #define I2S_TX_TDM_CHAN15_EN_V 0x1 794 #define I2S_TX_TDM_CHAN15_EN_S 15 795 /* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ 796 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 797 Disable just output 0 in this channel.*/ 798 #define I2S_TX_TDM_CHAN14_EN (BIT(14)) 799 #define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) 800 #define I2S_TX_TDM_CHAN14_EN_V 0x1 801 #define I2S_TX_TDM_CHAN14_EN_S 14 802 /* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ 803 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 804 Disable just output 0 in this channel.*/ 805 #define I2S_TX_TDM_CHAN13_EN (BIT(13)) 806 #define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) 807 #define I2S_TX_TDM_CHAN13_EN_V 0x1 808 #define I2S_TX_TDM_CHAN13_EN_S 13 809 /* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ 810 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 811 Disable just output 0 in this channel.*/ 812 #define I2S_TX_TDM_CHAN12_EN (BIT(12)) 813 #define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) 814 #define I2S_TX_TDM_CHAN12_EN_V 0x1 815 #define I2S_TX_TDM_CHAN12_EN_S 12 816 /* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ 817 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 818 Disable just output 0 in this channel.*/ 819 #define I2S_TX_TDM_CHAN11_EN (BIT(11)) 820 #define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) 821 #define I2S_TX_TDM_CHAN11_EN_V 0x1 822 #define I2S_TX_TDM_CHAN11_EN_S 11 823 /* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ 824 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 825 Disable just output 0 in this channel.*/ 826 #define I2S_TX_TDM_CHAN10_EN (BIT(10)) 827 #define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) 828 #define I2S_TX_TDM_CHAN10_EN_V 0x1 829 #define I2S_TX_TDM_CHAN10_EN_S 10 830 /* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ 831 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 832 Disable just output 0 in this channel.*/ 833 #define I2S_TX_TDM_CHAN9_EN (BIT(9)) 834 #define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) 835 #define I2S_TX_TDM_CHAN9_EN_V 0x1 836 #define I2S_TX_TDM_CHAN9_EN_S 9 837 /* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ 838 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 839 Disable just output 0 in this channel.*/ 840 #define I2S_TX_TDM_CHAN8_EN (BIT(8)) 841 #define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) 842 #define I2S_TX_TDM_CHAN8_EN_V 0x1 843 #define I2S_TX_TDM_CHAN8_EN_S 8 844 /* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ 845 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 846 Disable just output 0 in this channel.*/ 847 #define I2S_TX_TDM_CHAN7_EN (BIT(7)) 848 #define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) 849 #define I2S_TX_TDM_CHAN7_EN_V 0x1 850 #define I2S_TX_TDM_CHAN7_EN_S 7 851 /* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ 852 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 853 Disable just output 0 in this channel.*/ 854 #define I2S_TX_TDM_CHAN6_EN (BIT(6)) 855 #define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) 856 #define I2S_TX_TDM_CHAN6_EN_V 0x1 857 #define I2S_TX_TDM_CHAN6_EN_S 6 858 /* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ 859 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 860 Disable just output 0 in this channel.*/ 861 #define I2S_TX_TDM_CHAN5_EN (BIT(5)) 862 #define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) 863 #define I2S_TX_TDM_CHAN5_EN_V 0x1 864 #define I2S_TX_TDM_CHAN5_EN_S 5 865 /* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ 866 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 867 Disable just output 0 in this channel.*/ 868 #define I2S_TX_TDM_CHAN4_EN (BIT(4)) 869 #define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) 870 #define I2S_TX_TDM_CHAN4_EN_V 0x1 871 #define I2S_TX_TDM_CHAN4_EN_S 4 872 /* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ 873 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 874 Disable just output 0 in this channel.*/ 875 #define I2S_TX_TDM_CHAN3_EN (BIT(3)) 876 #define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) 877 #define I2S_TX_TDM_CHAN3_EN_V 0x1 878 #define I2S_TX_TDM_CHAN3_EN_S 3 879 /* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ 880 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 881 Disable just output 0 in this channel.*/ 882 #define I2S_TX_TDM_CHAN2_EN (BIT(2)) 883 #define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) 884 #define I2S_TX_TDM_CHAN2_EN_V 0x1 885 #define I2S_TX_TDM_CHAN2_EN_S 2 886 /* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ 887 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 888 Disable just output 0 in this channel.*/ 889 #define I2S_TX_TDM_CHAN1_EN (BIT(1)) 890 #define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) 891 #define I2S_TX_TDM_CHAN1_EN_V 0x1 892 #define I2S_TX_TDM_CHAN1_EN_S 1 893 /* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ 894 /*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: 895 Disable just output 0 in this channel.*/ 896 #define I2S_TX_TDM_CHAN0_EN (BIT(0)) 897 #define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) 898 #define I2S_TX_TDM_CHAN0_EN_V 0x1 899 #define I2S_TX_TDM_CHAN0_EN_S 0 900 901 #define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058) 902 /* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ 903 /*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay 904 by pos edge. 2: delay by neg edge. 3: not used.*/ 905 #define I2S_RX_BCK_IN_DM 0x00000003 906 #define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V)<<(I2S_RX_BCK_IN_DM_S)) 907 #define I2S_RX_BCK_IN_DM_V 0x3 908 #define I2S_RX_BCK_IN_DM_S 28 909 /* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ 910 /*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay 911 by pos edge. 2: delay by neg edge. 3: not used.*/ 912 #define I2S_RX_WS_IN_DM 0x00000003 913 #define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V)<<(I2S_RX_WS_IN_DM_S)) 914 #define I2S_RX_WS_IN_DM_V 0x3 915 #define I2S_RX_WS_IN_DM_S 24 916 /* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ 917 /*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay 918 by pos edge. 2: delay by neg edge. 3: not used.*/ 919 #define I2S_RX_BCK_OUT_DM 0x00000003 920 #define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V)<<(I2S_RX_BCK_OUT_DM_S)) 921 #define I2S_RX_BCK_OUT_DM_V 0x3 922 #define I2S_RX_BCK_OUT_DM_S 20 923 /* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ 924 /*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay 925 by pos edge. 2: delay by neg edge. 3: not used.*/ 926 #define I2S_RX_WS_OUT_DM 0x00000003 927 #define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V)<<(I2S_RX_WS_OUT_DM_S)) 928 #define I2S_RX_WS_OUT_DM_V 0x3 929 #define I2S_RX_WS_OUT_DM_S 16 930 /* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 931 /*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay 932 by pos edge. 2: delay by neg edge. 3: not used.*/ 933 #define I2S_RX_SD_IN_DM 0x00000003 934 #define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V)<<(I2S_RX_SD_IN_DM_S)) 935 #define I2S_RX_SD_IN_DM_V 0x3 936 #define I2S_RX_SD_IN_DM_S 0 937 938 #define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C) 939 /* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ 940 /*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay 941 by pos edge. 2: delay by neg edge. 3: not used.*/ 942 #define I2S_TX_BCK_IN_DM 0x00000003 943 #define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V)<<(I2S_TX_BCK_IN_DM_S)) 944 #define I2S_TX_BCK_IN_DM_V 0x3 945 #define I2S_TX_BCK_IN_DM_S 28 946 /* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ 947 /*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay 948 by pos edge. 2: delay by neg edge. 3: not used.*/ 949 #define I2S_TX_WS_IN_DM 0x00000003 950 #define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V)<<(I2S_TX_WS_IN_DM_S)) 951 #define I2S_TX_WS_IN_DM_V 0x3 952 #define I2S_TX_WS_IN_DM_S 24 953 /* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ 954 /*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay 955 by pos edge. 2: delay by neg edge. 3: not used.*/ 956 #define I2S_TX_BCK_OUT_DM 0x00000003 957 #define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V)<<(I2S_TX_BCK_OUT_DM_S)) 958 #define I2S_TX_BCK_OUT_DM_V 0x3 959 #define I2S_TX_BCK_OUT_DM_S 20 960 /* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ 961 /*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay 962 by pos edge. 2: delay by neg edge. 3: not used.*/ 963 #define I2S_TX_WS_OUT_DM 0x00000003 964 #define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V)<<(I2S_TX_WS_OUT_DM_S)) 965 #define I2S_TX_WS_OUT_DM_V 0x3 966 #define I2S_TX_WS_OUT_DM_S 16 967 /* I2S_TX_SD1_OUT_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ 968 /*description: The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: 969 delay by neg edge. 3: not used..*/ 970 #define I2S_TX_SD1_OUT_DM 0x00000003 971 #define I2S_TX_SD1_OUT_DM_M ((I2S_TX_SD1_OUT_DM_V)<<(I2S_TX_SD1_OUT_DM_S)) 972 #define I2S_TX_SD1_OUT_DM_V 0x3 973 #define I2S_TX_SD1_OUT_DM_S 4 974 /* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ 975 /*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay 976 by pos edge. 2: delay by neg edge. 3: not used.*/ 977 #define I2S_TX_SD_OUT_DM 0x00000003 978 #define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V)<<(I2S_TX_SD_OUT_DM_S)) 979 #define I2S_TX_SD_OUT_DM_V 0x3 980 #define I2S_TX_SD_OUT_DM_S 0 981 982 #define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) 983 /* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ 984 /*description: The enable bit for FIFO timeout*/ 985 #define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) 986 #define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) 987 #define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 988 #define I2S_LC_FIFO_TIMEOUT_ENA_S 11 989 /* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ 990 /*description: The bits are used to scale tick counter threshold. The tick counter 991 is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ 992 #define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 993 #define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S)) 994 #define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 995 #define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 996 /* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ 997 /*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt 998 will be triggered when fifo hung counter is equal to this value*/ 999 #define I2S_LC_FIFO_TIMEOUT 0x000000FF 1000 #define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S)) 1001 #define I2S_LC_FIFO_TIMEOUT_V 0xFF 1002 #define I2S_LC_FIFO_TIMEOUT_S 0 1003 1004 #define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064) 1005 /* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */ 1006 /*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ 1007 #define I2S_RX_EOF_NUM 0x00000FFF 1008 #define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S)) 1009 #define I2S_RX_EOF_NUM_V 0xFFF 1010 #define I2S_RX_EOF_NUM_S 0 1011 1012 #define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068) 1013 /* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ 1014 /*description: the right channel or left channel put out constant value stored 1015 in this register according to tx_chan_mod and reg_tx_msb_right*/ 1016 #define I2S_SINGLE_DATA 0xFFFFFFFF 1017 #define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V)<<(I2S_SINGLE_DATA_S)) 1018 #define I2S_SINGLE_DATA_V 0xFFFFFFFF 1019 #define I2S_SINGLE_DATA_S 0 1020 1021 #define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C) 1022 /* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ 1023 /*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/ 1024 #define I2S_TX_IDLE (BIT(0)) 1025 #define I2S_TX_IDLE_M (BIT(0)) 1026 #define I2S_TX_IDLE_V 0x1 1027 #define I2S_TX_IDLE_S 0 1028 1029 #define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080) 1030 /* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */ 1031 /*description: Version control register*/ 1032 #define I2S_DATE 0x0FFFFFFF 1033 #define I2S_DATE_M ((I2S_DATE_V)<<(I2S_DATE_S)) 1034 #define I2S_DATE_V 0xFFFFFFF 1035 #define I2S_DATE_S 0 1036 1037 #ifdef __cplusplus 1038 } 1039 #endif 1040 1041 1042 1043 #endif /*_SOC_I2S_REG_H_ */ 1044
