1 /** 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Interrupt registers */ 14 /** Type of int_raw register 15 * I2S interrupt raw register, valid in level. 16 */ 17 typedef union { 18 struct { 19 /** rx_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; 20 * The raw interrupt status bit for the i2s_rx_done_int interrupt 21 */ 22 uint32_t rx_done_int_raw:1; 23 /** tx_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; 24 * The raw interrupt status bit for the i2s_tx_done_int interrupt 25 */ 26 uint32_t tx_done_int_raw:1; 27 /** rx_hung_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; 28 * The raw interrupt status bit for the i2s_rx_hung_int interrupt 29 */ 30 uint32_t rx_hung_int_raw:1; 31 /** tx_hung_int_raw : RO/WTC/SS; bitpos: [3]; default: 0; 32 * The raw interrupt status bit for the i2s_tx_hung_int interrupt 33 */ 34 uint32_t tx_hung_int_raw:1; 35 uint32_t reserved_4:28; 36 }; 37 uint32_t val; 38 } i2s_int_raw_reg_t; 39 40 /** Type of int_st register 41 * I2S interrupt status register. 42 */ 43 typedef union { 44 struct { 45 /** rx_done_int_st : RO; bitpos: [0]; default: 0; 46 * The masked interrupt status bit for the i2s_rx_done_int interrupt 47 */ 48 uint32_t rx_done_int_st:1; 49 /** tx_done_int_st : RO; bitpos: [1]; default: 0; 50 * The masked interrupt status bit for the i2s_tx_done_int interrupt 51 */ 52 uint32_t tx_done_int_st:1; 53 /** rx_hung_int_st : RO; bitpos: [2]; default: 0; 54 * The masked interrupt status bit for the i2s_rx_hung_int interrupt 55 */ 56 uint32_t rx_hung_int_st:1; 57 /** tx_hung_int_st : RO; bitpos: [3]; default: 0; 58 * The masked interrupt status bit for the i2s_tx_hung_int interrupt 59 */ 60 uint32_t tx_hung_int_st:1; 61 uint32_t reserved_4:28; 62 }; 63 uint32_t val; 64 } i2s_int_st_reg_t; 65 66 /** Type of int_ena register 67 * I2S interrupt enable register. 68 */ 69 typedef union { 70 struct { 71 /** rx_done_int_ena : R/W; bitpos: [0]; default: 0; 72 * The interrupt enable bit for the i2s_rx_done_int interrupt 73 */ 74 uint32_t rx_done_int_ena:1; 75 /** tx_done_int_ena : R/W; bitpos: [1]; default: 0; 76 * The interrupt enable bit for the i2s_tx_done_int interrupt 77 */ 78 uint32_t tx_done_int_ena:1; 79 /** rx_hung_int_ena : R/W; bitpos: [2]; default: 0; 80 * The interrupt enable bit for the i2s_rx_hung_int interrupt 81 */ 82 uint32_t rx_hung_int_ena:1; 83 /** tx_hung_int_ena : R/W; bitpos: [3]; default: 0; 84 * The interrupt enable bit for the i2s_tx_hung_int interrupt 85 */ 86 uint32_t tx_hung_int_ena:1; 87 uint32_t reserved_4:28; 88 }; 89 uint32_t val; 90 } i2s_int_ena_reg_t; 91 92 /** Type of int_clr register 93 * I2S interrupt clear register. 94 */ 95 typedef union { 96 struct { 97 /** rx_done_int_clr : WT; bitpos: [0]; default: 0; 98 * Set this bit to clear the i2s_rx_done_int interrupt 99 */ 100 uint32_t rx_done_int_clr:1; 101 /** tx_done_int_clr : WT; bitpos: [1]; default: 0; 102 * Set this bit to clear the i2s_tx_done_int interrupt 103 */ 104 uint32_t tx_done_int_clr:1; 105 /** rx_hung_int_clr : WT; bitpos: [2]; default: 0; 106 * Set this bit to clear the i2s_rx_hung_int interrupt 107 */ 108 uint32_t rx_hung_int_clr:1; 109 /** tx_hung_int_clr : WT; bitpos: [3]; default: 0; 110 * Set this bit to clear the i2s_tx_hung_int interrupt 111 */ 112 uint32_t tx_hung_int_clr:1; 113 uint32_t reserved_4:28; 114 }; 115 uint32_t val; 116 } i2s_int_clr_reg_t; 117 118 119 /** Group: RX Control and configuration registers */ 120 /** Type of rx_conf register 121 * I2S RX configure register 122 */ 123 typedef union { 124 struct { 125 /** rx_reset : WT; bitpos: [0]; default: 0; 126 * Set this bit to reset receiver 127 */ 128 uint32_t rx_reset:1; 129 /** rx_fifo_reset : WT; bitpos: [1]; default: 0; 130 * Set this bit to reset Rx AFIFO 131 */ 132 uint32_t rx_fifo_reset:1; 133 /** rx_start : R/W/SC; bitpos: [2]; default: 0; 134 * Set this bit to start receiving data 135 */ 136 uint32_t rx_start:1; 137 /** rx_slave_mod : R/W; bitpos: [3]; default: 0; 138 * Set this bit to enable slave receiver mode 139 */ 140 uint32_t rx_slave_mod:1; 141 /** rx_stop_mode : R/W; bitpos: [5:4]; default: 0; 142 * 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 143 * 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full. 144 */ 145 uint32_t rx_stop_mode:2; 146 /** rx_mono : R/W; bitpos: [6]; default: 0; 147 * Set this bit to enable receiver in mono mode 148 */ 149 uint32_t rx_mono:1; 150 /** rx_big_endian : R/W; bitpos: [7]; default: 0; 151 * I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value. 152 */ 153 uint32_t rx_big_endian:1; 154 /** rx_update : R/W/SC; bitpos: [8]; default: 0; 155 * Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This 156 * bit will be cleared by hardware after update register done. 157 */ 158 uint32_t rx_update:1; 159 /** rx_mono_fst_vld : R/W; bitpos: [9]; default: 1; 160 * 1: The first channel data value is valid in I2S RX mono mode. 0: The second 161 * channel data value is valid in I2S RX mono mode. 162 */ 163 uint32_t rx_mono_fst_vld:1; 164 /** rx_pcm_conf : R/W; bitpos: [11:10]; default: 1; 165 * I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 166 * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 167 */ 168 uint32_t rx_pcm_conf:2; 169 /** rx_pcm_bypass : R/W; bitpos: [12]; default: 1; 170 * Set this bit to bypass Compress/Decompress module for received data. 171 */ 172 uint32_t rx_pcm_bypass:1; 173 /** rx_msb_shift : R/W; bitpos: [13]; default: 1; 174 * Set this bit to enable receiver in Phillips standard mode 175 */ 176 uint32_t rx_msb_shift:1; 177 uint32_t reserved_14:1; 178 /** rx_left_align : R/W; bitpos: [15]; default: 1; 179 * 1: I2S RX left alignment mode. 0: I2S RX right alignment mode. 180 */ 181 uint32_t rx_left_align:1; 182 /** rx_24_fill_en : R/W; bitpos: [16]; default: 0; 183 * 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits. 184 */ 185 uint32_t rx_24_fill_en:1; 186 /** rx_ws_idle_pol : R/W; bitpos: [17]; default: 0; 187 * 0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 188 * 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. 189 */ 190 uint32_t rx_ws_idle_pol:1; 191 /** rx_bit_order : R/W; bitpos: [18]; default: 0; 192 * I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB 193 * is received first. 194 */ 195 uint32_t rx_bit_order:1; 196 /** rx_tdm_en : R/W; bitpos: [19]; default: 0; 197 * 1: Enable I2S TDM Rx mode . 0: Disable. 198 */ 199 uint32_t rx_tdm_en:1; 200 /** rx_pdm_en : R/W; bitpos: [20]; default: 0; 201 * 1: Enable I2S PDM Rx mode . 0: Disable. 202 */ 203 uint32_t rx_pdm_en:1; 204 /** rx_bck_div_num : R/W; bitpos: [26:21]; default: 6; 205 * Bit clock configuration bits in receiver mode. 206 */ 207 uint32_t rx_bck_div_num:6; 208 uint32_t reserved_27:5; 209 }; 210 uint32_t val; 211 } i2s_rx_conf_reg_t; 212 213 /** Type of rx_conf1 register 214 * I2S RX configure register 1 215 */ 216 typedef union { 217 struct { 218 /** rx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; 219 * The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * 220 * T_bck 221 */ 222 uint32_t rx_tdm_ws_width:9; 223 uint32_t reserved_9:5; 224 /** rx_bits_mod : R/W; bitpos: [18:14]; default: 15; 225 * Set the bits to configure the valid data bit length of I2S receiver channel. 7: all 226 * the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 227 * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid 228 * channel data is in 32-bit-mode. 229 */ 230 uint32_t rx_bits_mod:5; 231 /** rx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; 232 * I2S Rx half sample bits -1. 233 */ 234 uint32_t rx_half_sample_bits:8; 235 /** rx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; 236 * The Rx bit number for each channel minus 1in TDM mode. 237 */ 238 uint32_t rx_tdm_chan_bits:5; 239 }; 240 uint32_t val; 241 } i2s_rx_conf1_reg_t; 242 243 /** Type of rx_clkm_conf register 244 * I2S RX clock configure register 245 */ 246 typedef union { 247 struct { 248 /** rx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; 249 * Integral I2S clock divider value 250 */ 251 uint32_t rx_clkm_div_num:8; 252 uint32_t reserved_8:18; 253 /** rx_clk_active : R/W; bitpos: [26]; default: 0; 254 * I2S Rx module clock enable signal. 255 */ 256 uint32_t rx_clk_active:1; 257 /** rx_clk_sel : R/W; bitpos: [28:27]; default: 0; 258 * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 259 */ 260 uint32_t rx_clk_sel:2; 261 /** mclk_sel : R/W; bitpos: [29]; default: 0; 262 * 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as 263 * I2S_MCLK_OUT. 264 */ 265 uint32_t mclk_sel:1; 266 uint32_t reserved_30:2; 267 }; 268 uint32_t val; 269 } i2s_rx_clkm_conf_reg_t; 270 271 /** Type of tx_pcm2pdm_conf register 272 * I2S TX PCM2PDM configuration register 273 */ 274 typedef union { 275 struct { 276 /** tx_pdm_hp_bypass : R/W; bitpos: [0]; default: 0; 277 * I2S TX PDM bypass hp filter or not. The option has been removed. 278 */ 279 uint32_t tx_pdm_hp_bypass:1; 280 /** tx_pdm_sinc_osr2 : R/W; bitpos: [4:1]; default: 2; 281 * I2S TX PDM OSR2 value 282 */ 283 uint32_t tx_pdm_sinc_osr2:4; 284 /** tx_pdm_prescale : R/W; bitpos: [12:5]; default: 0; 285 * I2S TX PDM prescale for sigmadelta 286 */ 287 uint32_t tx_pdm_prescale:8; 288 /** tx_pdm_hp_in_shift : R/W; bitpos: [14:13]; default: 1; 289 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 290 */ 291 uint32_t tx_pdm_hp_in_shift:2; 292 /** tx_pdm_lp_in_shift : R/W; bitpos: [16:15]; default: 1; 293 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 294 */ 295 uint32_t tx_pdm_lp_in_shift:2; 296 /** tx_pdm_sinc_in_shift : R/W; bitpos: [18:17]; default: 1; 297 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 298 */ 299 uint32_t tx_pdm_sinc_in_shift:2; 300 /** tx_pdm_sigmadelta_in_shift : R/W; bitpos: [20:19]; default: 1; 301 * I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4 302 */ 303 uint32_t tx_pdm_sigmadelta_in_shift:2; 304 /** tx_pdm_sigmadelta_dither2 : R/W; bitpos: [21]; default: 0; 305 * I2S TX PDM sigmadelta dither2 value 306 */ 307 uint32_t tx_pdm_sigmadelta_dither2:1; 308 /** tx_pdm_sigmadelta_dither : R/W; bitpos: [22]; default: 1; 309 * I2S TX PDM sigmadelta dither value 310 */ 311 uint32_t tx_pdm_sigmadelta_dither:1; 312 /** tx_pdm_dac_2out_en : R/W; bitpos: [23]; default: 0; 313 * I2S TX PDM dac mode enable 314 */ 315 uint32_t tx_pdm_dac_2out_en:1; 316 /** tx_pdm_dac_mode_en : R/W; bitpos: [24]; default: 0; 317 * I2S TX PDM dac 2channel enable 318 */ 319 uint32_t tx_pdm_dac_mode_en:1; 320 /** pcm2pdm_conv_en : R/W; bitpos: [25]; default: 0; 321 * I2S TX PDM Converter enable 322 */ 323 uint32_t pcm2pdm_conv_en:1; 324 uint32_t reserved_26:6; 325 }; 326 uint32_t val; 327 } i2s_tx_pcm2pdm_conf_reg_t; 328 329 /** Type of tx_pcm2pdm_conf1 register 330 * I2S TX PCM2PDM configuration register 331 */ 332 typedef union { 333 struct { 334 /** tx_pdm_fp : R/W; bitpos: [9:0]; default: 960; 335 * I2S TX PDM Fp 336 */ 337 uint32_t tx_pdm_fp:10; 338 /** tx_pdm_fs : R/W; bitpos: [19:10]; default: 480; 339 * I2S TX PDM Fs 340 */ 341 uint32_t tx_pdm_fs:10; 342 /** tx_iir_hp_mult12_5 : R/W; bitpos: [22:20]; default: 7; 343 * The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + 344 * I2S_TX_IIR_HP_MULT12_5[2:0]) 345 */ 346 uint32_t tx_iir_hp_mult12_5:3; 347 /** tx_iir_hp_mult12_0 : R/W; bitpos: [25:23]; default: 7; 348 * The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + 349 * I2S_TX_IIR_HP_MULT12_0[2:0]) 350 */ 351 uint32_t tx_iir_hp_mult12_0:3; 352 uint32_t reserved_26:6; 353 }; 354 uint32_t val; 355 } i2s_tx_pcm2pdm_conf1_reg_t; 356 357 /** Type of rx_tdm_ctrl register 358 * I2S TX TDM mode control register 359 */ 360 typedef union { 361 struct { 362 /** rx_tdm_pdm_chan0_en : R/W; bitpos: [0]; default: 1; 363 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 364 * input 0 in this channel. 365 */ 366 uint32_t rx_tdm_pdm_chan0_en:1; 367 /** rx_tdm_pdm_chan1_en : R/W; bitpos: [1]; default: 1; 368 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 369 * input 0 in this channel. 370 */ 371 uint32_t rx_tdm_pdm_chan1_en:1; 372 /** rx_tdm_pdm_chan2_en : R/W; bitpos: [2]; default: 1; 373 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 374 * input 0 in this channel. 375 */ 376 uint32_t rx_tdm_pdm_chan2_en:1; 377 /** rx_tdm_pdm_chan3_en : R/W; bitpos: [3]; default: 1; 378 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 379 * input 0 in this channel. 380 */ 381 uint32_t rx_tdm_pdm_chan3_en:1; 382 /** rx_tdm_pdm_chan4_en : R/W; bitpos: [4]; default: 1; 383 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 384 * input 0 in this channel. 385 */ 386 uint32_t rx_tdm_pdm_chan4_en:1; 387 /** rx_tdm_pdm_chan5_en : R/W; bitpos: [5]; default: 1; 388 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 389 * input 0 in this channel. 390 */ 391 uint32_t rx_tdm_pdm_chan5_en:1; 392 /** rx_tdm_pdm_chan6_en : R/W; bitpos: [6]; default: 1; 393 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 394 * input 0 in this channel. 395 */ 396 uint32_t rx_tdm_pdm_chan6_en:1; 397 /** rx_tdm_pdm_chan7_en : R/W; bitpos: [7]; default: 1; 398 * 1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just 399 * input 0 in this channel. 400 */ 401 uint32_t rx_tdm_pdm_chan7_en:1; 402 /** rx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; 403 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 404 * in this channel. 405 */ 406 uint32_t rx_tdm_chan8_en:1; 407 /** rx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; 408 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 409 * in this channel. 410 */ 411 uint32_t rx_tdm_chan9_en:1; 412 /** rx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; 413 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 414 * in this channel. 415 */ 416 uint32_t rx_tdm_chan10_en:1; 417 /** rx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; 418 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 419 * in this channel. 420 */ 421 uint32_t rx_tdm_chan11_en:1; 422 /** rx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; 423 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 424 * in this channel. 425 */ 426 uint32_t rx_tdm_chan12_en:1; 427 /** rx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; 428 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 429 * in this channel. 430 */ 431 uint32_t rx_tdm_chan13_en:1; 432 /** rx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; 433 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 434 * in this channel. 435 */ 436 uint32_t rx_tdm_chan14_en:1; 437 /** rx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; 438 * 1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 439 * in this channel. 440 */ 441 uint32_t rx_tdm_chan15_en:1; 442 /** rx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; 443 * The total channel number of I2S TX TDM mode. 444 */ 445 uint32_t rx_tdm_tot_chan_num:4; 446 uint32_t reserved_20:12; 447 }; 448 uint32_t val; 449 } i2s_rx_tdm_ctrl_reg_t; 450 451 /** Type of rx_eof_num register 452 * I2S RX data number control register. 453 */ 454 typedef union { 455 struct { 456 /** rx_eof_num : R/W; bitpos: [11:0]; default: 64; 457 * The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 458 * 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel. 459 */ 460 uint32_t rx_eof_num:12; 461 uint32_t reserved_12:20; 462 }; 463 uint32_t val; 464 } i2s_rx_eof_num_reg_t; 465 466 467 /** Group: TX Control and configuration registers */ 468 /** Type of tx_conf register 469 * I2S TX configure register 470 */ 471 typedef union { 472 struct { 473 /** tx_reset : WT; bitpos: [0]; default: 0; 474 * Set this bit to reset transmitter 475 */ 476 uint32_t tx_reset:1; 477 /** tx_fifo_reset : WT; bitpos: [1]; default: 0; 478 * Set this bit to reset Tx AFIFO 479 */ 480 uint32_t tx_fifo_reset:1; 481 /** tx_start : R/W/SC; bitpos: [2]; default: 0; 482 * Set this bit to start transmitting data 483 */ 484 uint32_t tx_start:1; 485 /** tx_slave_mod : R/W; bitpos: [3]; default: 0; 486 * Set this bit to enable slave transmitter mode 487 */ 488 uint32_t tx_slave_mod:1; 489 /** tx_stop_en : R/W; bitpos: [4]; default: 1; 490 * Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy 491 */ 492 uint32_t tx_stop_en:1; 493 /** tx_chan_equal : R/W; bitpos: [5]; default: 0; 494 * 1: The value of Left channel data is equal to the value of right channel data in 495 * I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is 496 * reg_i2s_single_data in I2S TX mono mode or TDM channel select mode. 497 */ 498 uint32_t tx_chan_equal:1; 499 /** tx_mono : R/W; bitpos: [6]; default: 0; 500 * Set this bit to enable transmitter in mono mode 501 */ 502 uint32_t tx_mono:1; 503 /** tx_big_endian : R/W; bitpos: [7]; default: 0; 504 * I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr 505 * value. 506 */ 507 uint32_t tx_big_endian:1; 508 /** tx_update : R/W/SC; bitpos: [8]; default: 0; 509 * Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This 510 * bit will be cleared by hardware after update register done. 511 */ 512 uint32_t tx_update:1; 513 /** tx_mono_fst_vld : R/W; bitpos: [9]; default: 1; 514 * 1: The first channel data value is valid in I2S TX mono mode. 0: The second 515 * channel data value is valid in I2S TX mono mode. 516 */ 517 uint32_t tx_mono_fst_vld:1; 518 /** tx_pcm_conf : R/W; bitpos: [11:10]; default: 0; 519 * I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 520 * (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. & 521 */ 522 uint32_t tx_pcm_conf:2; 523 /** tx_pcm_bypass : R/W; bitpos: [12]; default: 1; 524 * Set this bit to bypass Compress/Decompress module for transmitted data. 525 */ 526 uint32_t tx_pcm_bypass:1; 527 /** tx_msb_shift : R/W; bitpos: [13]; default: 1; 528 * Set this bit to enable transmitter in Phillips standard mode 529 */ 530 uint32_t tx_msb_shift:1; 531 /** tx_bck_no_dly : R/W; bitpos: [14]; default: 1; 532 * 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to 533 * generate pos/neg edge in master mode. 534 */ 535 uint32_t tx_bck_no_dly:1; 536 /** tx_left_align : R/W; bitpos: [15]; default: 1; 537 * 1: I2S TX left alignment mode. 0: I2S TX right alignment mode. 538 */ 539 uint32_t tx_left_align:1; 540 /** tx_24_fill_en : R/W; bitpos: [16]; default: 0; 541 * 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode 542 */ 543 uint32_t tx_24_fill_en:1; 544 /** tx_ws_idle_pol : R/W; bitpos: [17]; default: 0; 545 * 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: 546 * WS should be 1 when sending left channel data, and WS is 0in right channel. 547 */ 548 uint32_t tx_ws_idle_pol:1; 549 /** tx_bit_order : R/W; bitpos: [18]; default: 0; 550 * I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is 551 * sent first. 552 */ 553 uint32_t tx_bit_order:1; 554 /** tx_tdm_en : R/W; bitpos: [19]; default: 0; 555 * 1: Enable I2S TDM Tx mode . 0: Disable. 556 */ 557 uint32_t tx_tdm_en:1; 558 /** tx_pdm_en : R/W; bitpos: [20]; default: 0; 559 * 1: Enable I2S PDM Tx mode . 0: Disable. 560 */ 561 uint32_t tx_pdm_en:1; 562 /** tx_bck_div_num : R/W; bitpos: [26:21]; default: 6; 563 * Bit clock configuration bits in transmitter mode. 564 */ 565 uint32_t tx_bck_div_num:6; 566 /** tx_chan_mod : R/W; bitpos: [29:27]; default: 0; 567 * I2S transmitter channel mode configuration bits. 568 */ 569 uint32_t tx_chan_mod:3; 570 /** sig_loopback : R/W; bitpos: [30]; default: 0; 571 * Enable signal loop back mode with transmitter module and receiver module sharing 572 * the same WS and BCK signals. 573 */ 574 uint32_t sig_loopback:1; 575 uint32_t reserved_31:1; 576 }; 577 uint32_t val; 578 } i2s_tx_conf_reg_t; 579 580 /** Type of tx_conf1 register 581 * I2S TX configure register 1 582 */ 583 typedef union { 584 struct { 585 /** tx_tdm_ws_width : R/W; bitpos: [8:0]; default: 0; 586 * The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * 587 * T_bck 588 */ 589 uint32_t tx_tdm_ws_width:9; 590 uint32_t reserved_9:5; 591 /** tx_bits_mod : R/W; bitpos: [18:14]; default: 15; 592 * Set the bits to configure the valid data bit length of I2S transmitter channel. 7: 593 * all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 594 * 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid 595 * channel data is in 32-bit-mode. 596 */ 597 uint32_t tx_bits_mod:5; 598 /** tx_half_sample_bits : R/W; bitpos: [26:19]; default: 15; 599 * I2S Tx half sample bits -1. 600 */ 601 uint32_t tx_half_sample_bits:8; 602 /** tx_tdm_chan_bits : R/W; bitpos: [31:27]; default: 15; 603 * The Tx bit number for each channel minus 1in TDM mode. 604 */ 605 uint32_t tx_tdm_chan_bits:5; 606 }; 607 uint32_t val; 608 } i2s_tx_conf1_reg_t; 609 610 /** Type of tx_clkm_conf register 611 * I2S TX clock configure register 612 */ 613 typedef union { 614 struct { 615 /** tx_clkm_div_num : R/W; bitpos: [7:0]; default: 2; 616 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be 617 * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= 618 * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * 619 * (n+1)-div] + y * (n+1)-div. 620 */ 621 uint32_t tx_clkm_div_num:8; 622 uint32_t reserved_8:18; 623 /** tx_clk_active : R/W; bitpos: [26]; default: 0; 624 * I2S Tx module clock enable signal. 625 */ 626 uint32_t tx_clk_active:1; 627 /** tx_clk_sel : R/W; bitpos: [28:27]; default: 0; 628 * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: 629 * I2S_MCLK_in. 630 */ 631 uint32_t tx_clk_sel:2; 632 /** clk_en : R/W; bitpos: [29]; default: 0; 633 * Set this bit to enable clk gate 634 */ 635 uint32_t clk_en:1; 636 uint32_t reserved_30:2; 637 }; 638 uint32_t val; 639 } i2s_tx_clkm_conf_reg_t; 640 641 /** Type of tx_tdm_ctrl register 642 * I2S TX TDM mode control register 643 */ 644 typedef union { 645 struct { 646 /** tx_tdm_chan0_en : R/W; bitpos: [0]; default: 1; 647 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 648 * 0 in this channel. 649 */ 650 uint32_t tx_tdm_chan0_en:1; 651 /** tx_tdm_chan1_en : R/W; bitpos: [1]; default: 1; 652 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 653 * 0 in this channel. 654 */ 655 uint32_t tx_tdm_chan1_en:1; 656 /** tx_tdm_chan2_en : R/W; bitpos: [2]; default: 1; 657 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 658 * 0 in this channel. 659 */ 660 uint32_t tx_tdm_chan2_en:1; 661 /** tx_tdm_chan3_en : R/W; bitpos: [3]; default: 1; 662 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 663 * 0 in this channel. 664 */ 665 uint32_t tx_tdm_chan3_en:1; 666 /** tx_tdm_chan4_en : R/W; bitpos: [4]; default: 1; 667 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 668 * 0 in this channel. 669 */ 670 uint32_t tx_tdm_chan4_en:1; 671 /** tx_tdm_chan5_en : R/W; bitpos: [5]; default: 1; 672 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 673 * 0 in this channel. 674 */ 675 uint32_t tx_tdm_chan5_en:1; 676 /** tx_tdm_chan6_en : R/W; bitpos: [6]; default: 1; 677 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 678 * 0 in this channel. 679 */ 680 uint32_t tx_tdm_chan6_en:1; 681 /** tx_tdm_chan7_en : R/W; bitpos: [7]; default: 1; 682 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 683 * 0 in this channel. 684 */ 685 uint32_t tx_tdm_chan7_en:1; 686 /** tx_tdm_chan8_en : R/W; bitpos: [8]; default: 1; 687 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 688 * 0 in this channel. 689 */ 690 uint32_t tx_tdm_chan8_en:1; 691 /** tx_tdm_chan9_en : R/W; bitpos: [9]; default: 1; 692 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 693 * 0 in this channel. 694 */ 695 uint32_t tx_tdm_chan9_en:1; 696 /** tx_tdm_chan10_en : R/W; bitpos: [10]; default: 1; 697 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 698 * 0 in this channel. 699 */ 700 uint32_t tx_tdm_chan10_en:1; 701 /** tx_tdm_chan11_en : R/W; bitpos: [11]; default: 1; 702 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 703 * 0 in this channel. 704 */ 705 uint32_t tx_tdm_chan11_en:1; 706 /** tx_tdm_chan12_en : R/W; bitpos: [12]; default: 1; 707 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 708 * 0 in this channel. 709 */ 710 uint32_t tx_tdm_chan12_en:1; 711 /** tx_tdm_chan13_en : R/W; bitpos: [13]; default: 1; 712 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 713 * 0 in this channel. 714 */ 715 uint32_t tx_tdm_chan13_en:1; 716 /** tx_tdm_chan14_en : R/W; bitpos: [14]; default: 1; 717 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 718 * 0 in this channel. 719 */ 720 uint32_t tx_tdm_chan14_en:1; 721 /** tx_tdm_chan15_en : R/W; bitpos: [15]; default: 1; 722 * 1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 723 * 0 in this channel. 724 */ 725 uint32_t tx_tdm_chan15_en:1; 726 /** tx_tdm_tot_chan_num : R/W; bitpos: [19:16]; default: 0; 727 * The total channel number of I2S TX TDM mode. 728 */ 729 uint32_t tx_tdm_tot_chan_num:4; 730 /** tx_tdm_skip_msk_en : R/W; bitpos: [20]; default: 0; 731 * When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and 732 * only the data of the enabled channels is sent, then this bit should be set. Clear 733 * it when all the data stored in DMA TX buffer is for enabled channels. 734 */ 735 uint32_t tx_tdm_skip_msk_en:1; 736 uint32_t reserved_21:11; 737 }; 738 uint32_t val; 739 } i2s_tx_tdm_ctrl_reg_t; 740 741 742 /** Group: RX clock and timing registers */ 743 /** Type of rx_clkm_div_conf register 744 * I2S RX module clock divider configure register 745 */ 746 typedef union { 747 struct { 748 /** rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 749 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of 750 * I2S_RX_CLKM_DIV_Z is (a-b). 751 */ 752 uint32_t rx_clkm_div_z:9; 753 /** rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 754 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 755 * I2S_RX_CLKM_DIV_Y is (a%(a-b)). 756 */ 757 uint32_t rx_clkm_div_y:9; 758 /** rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 759 * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 760 * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 761 */ 762 uint32_t rx_clkm_div_x:9; 763 /** rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 764 * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 765 * I2S_RX_CLKM_DIV_YN1 is 1. 766 */ 767 uint32_t rx_clkm_div_yn1:1; 768 uint32_t reserved_28:4; 769 }; 770 uint32_t val; 771 } i2s_rx_clkm_div_conf_reg_t; 772 773 /** Type of rx_timing register 774 * I2S RX timing control register 775 */ 776 typedef union { 777 struct { 778 /** rx_sd_in_dm : R/W; bitpos: [1:0]; default: 0; 779 * The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: 780 * delay by neg edge. 3: not used. 781 */ 782 uint32_t rx_sd_in_dm:2; 783 uint32_t reserved_2:14; 784 /** rx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; 785 * The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: 786 * delay by neg edge. 3: not used. 787 */ 788 uint32_t rx_ws_out_dm:2; 789 uint32_t reserved_18:2; 790 /** rx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; 791 * The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: 792 * delay by neg edge. 3: not used. 793 */ 794 uint32_t rx_bck_out_dm:2; 795 uint32_t reserved_22:2; 796 /** rx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; 797 * The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: 798 * delay by neg edge. 3: not used. 799 */ 800 uint32_t rx_ws_in_dm:2; 801 uint32_t reserved_26:2; 802 /** rx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; 803 * The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: 804 * delay by neg edge. 3: not used. 805 */ 806 uint32_t rx_bck_in_dm:2; 807 uint32_t reserved_30:2; 808 }; 809 uint32_t val; 810 } i2s_rx_timing_reg_t; 811 812 813 /** Group: TX clock and timing registers */ 814 /** Type of tx_clkm_div_conf register 815 * I2S TX module clock divider configure register 816 */ 817 typedef union { 818 struct { 819 /** tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 820 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of 821 * I2S_TX_CLKM_DIV_Z is (a-b). 822 */ 823 uint32_t tx_clkm_div_z:9; 824 /** tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 825 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 826 * I2S_TX_CLKM_DIV_Y is (a%(a-b)). 827 */ 828 uint32_t tx_clkm_div_y:9; 829 /** tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 830 * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 831 * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 832 */ 833 uint32_t tx_clkm_div_x:9; 834 /** tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 835 * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 836 * I2S_TX_CLKM_DIV_YN1 is 1. 837 */ 838 uint32_t tx_clkm_div_yn1:1; 839 uint32_t reserved_28:4; 840 }; 841 uint32_t val; 842 } i2s_tx_clkm_div_conf_reg_t; 843 844 /** Type of tx_timing register 845 * I2S TX timing control register 846 */ 847 typedef union { 848 struct { 849 /** tx_sd_out_dm : R/W; bitpos: [1:0]; default: 0; 850 * The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: 851 * delay by neg edge. 3: not used. 852 */ 853 uint32_t tx_sd_out_dm:2; 854 uint32_t reserved_2:2; 855 /** tx_sd1_out_dm : R/W; bitpos: [5:4]; default: 0; 856 * The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: 857 * delay by neg edge. 3: not used. 858 */ 859 uint32_t tx_sd1_out_dm:2; 860 uint32_t reserved_6:10; 861 /** tx_ws_out_dm : R/W; bitpos: [17:16]; default: 0; 862 * The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: 863 * delay by neg edge. 3: not used. 864 */ 865 uint32_t tx_ws_out_dm:2; 866 uint32_t reserved_18:2; 867 /** tx_bck_out_dm : R/W; bitpos: [21:20]; default: 0; 868 * The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: 869 * delay by neg edge. 3: not used. 870 */ 871 uint32_t tx_bck_out_dm:2; 872 uint32_t reserved_22:2; 873 /** tx_ws_in_dm : R/W; bitpos: [25:24]; default: 0; 874 * The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: 875 * delay by neg edge. 3: not used. 876 */ 877 uint32_t tx_ws_in_dm:2; 878 uint32_t reserved_26:2; 879 /** tx_bck_in_dm : R/W; bitpos: [29:28]; default: 0; 880 * The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: 881 * delay by neg edge. 3: not used. 882 */ 883 uint32_t tx_bck_in_dm:2; 884 uint32_t reserved_30:2; 885 }; 886 uint32_t val; 887 } i2s_tx_timing_reg_t; 888 889 890 /** Group: Control and configuration registers */ 891 /** Type of lc_hung_conf register 892 * I2S HUNG configure register. 893 */ 894 typedef union { 895 struct { 896 /** lc_fifo_timeout : R/W; bitpos: [7:0]; default: 16; 897 * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered 898 * when fifo hung counter is equal to this value 899 */ 900 uint32_t lc_fifo_timeout:8; 901 /** lc_fifo_timeout_shift : R/W; bitpos: [10:8]; default: 0; 902 * The bits are used to scale tick counter threshold. The tick counter is reset when 903 * counter value >= 88000/2^i2s_lc_fifo_timeout_shift 904 */ 905 uint32_t lc_fifo_timeout_shift:3; 906 /** lc_fifo_timeout_ena : R/W; bitpos: [11]; default: 1; 907 * The enable bit for FIFO timeout 908 */ 909 uint32_t lc_fifo_timeout_ena:1; 910 uint32_t reserved_12:20; 911 }; 912 uint32_t val; 913 } i2s_lc_hung_conf_reg_t; 914 915 /** Type of conf_single_data register 916 * I2S signal data register 917 */ 918 typedef union { 919 struct { 920 /** single_data : R/W; bitpos: [31:0]; default: 0; 921 * The configured constant channel data to be sent out. 922 */ 923 uint32_t single_data:32; 924 }; 925 uint32_t val; 926 } i2s_conf_single_data_reg_t; 927 928 929 /** Group: TX status registers */ 930 /** Type of state register 931 * I2S TX status register 932 */ 933 typedef union { 934 struct { 935 /** tx_idle : RO; bitpos: [0]; default: 1; 936 * 1: i2s_tx is idle state. 0: i2s_tx is working. 937 */ 938 uint32_t tx_idle:1; 939 uint32_t reserved_1:31; 940 }; 941 uint32_t val; 942 } i2s_state_reg_t; 943 944 945 /** Group: ETM registers */ 946 /** Type of etm_conf register 947 * I2S ETM configure register 948 */ 949 typedef union { 950 struct { 951 /** etm_tx_send_word_num : R/W; bitpos: [9:0]; default: 64; 952 * I2S ETM send x words event. When sending word number of 953 * reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event. 954 */ 955 uint32_t etm_tx_send_word_num:10; 956 /** etm_rx_receive_word_num : R/W; bitpos: [19:10]; default: 64; 957 * I2S ETM receive x words event. When receiving word number of 958 * reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event. 959 */ 960 uint32_t etm_rx_receive_word_num:10; 961 uint32_t reserved_20:12; 962 }; 963 uint32_t val; 964 } i2s_etm_conf_reg_t; 965 966 967 /** Group: Version register */ 968 /** Type of date register 969 * Version control register 970 */ 971 typedef union { 972 struct { 973 /** date : R/W; bitpos: [27:0]; default: 35684944; 974 * I2S version control register 975 */ 976 uint32_t date:28; 977 uint32_t reserved_28:4; 978 }; 979 uint32_t val; 980 } i2s_date_reg_t; 981 982 983 typedef struct { 984 uint32_t reserved_000[3]; 985 volatile i2s_int_raw_reg_t int_raw; 986 volatile i2s_int_st_reg_t int_st; 987 volatile i2s_int_ena_reg_t int_ena; 988 volatile i2s_int_clr_reg_t int_clr; 989 uint32_t reserved_01c; 990 volatile i2s_rx_conf_reg_t rx_conf; 991 volatile i2s_tx_conf_reg_t tx_conf; 992 volatile i2s_rx_conf1_reg_t rx_conf1; 993 volatile i2s_tx_conf1_reg_t tx_conf1; 994 volatile i2s_rx_clkm_conf_reg_t rx_clkm_conf; 995 volatile i2s_tx_clkm_conf_reg_t tx_clkm_conf; 996 volatile i2s_rx_clkm_div_conf_reg_t rx_clkm_div_conf; 997 volatile i2s_tx_clkm_div_conf_reg_t tx_clkm_div_conf; 998 volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf; 999 volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1; 1000 uint32_t reserved_048[2]; 1001 volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl; 1002 volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl; 1003 volatile i2s_rx_timing_reg_t rx_timing; 1004 volatile i2s_tx_timing_reg_t tx_timing; 1005 volatile i2s_lc_hung_conf_reg_t lc_hung_conf; 1006 volatile i2s_rx_eof_num_reg_t rx_eof_num; 1007 volatile i2s_conf_single_data_reg_t conf_single_data; 1008 volatile i2s_state_reg_t state; 1009 volatile i2s_etm_conf_reg_t etm_conf; 1010 uint32_t reserved_074[3]; 1011 volatile i2s_date_reg_t date; 1012 } i2s_dev_t; 1013 1014 extern i2s_dev_t I2S0; 1015 1016 #ifndef __cplusplus 1017 _Static_assert(sizeof(i2s_dev_t) == 0x84, "Invalid size of i2s_dev_t structure"); 1018 #endif 1019 1020 #ifdef __cplusplus 1021 } 1022 #endif 1023
