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/Zephyr-latest/dts/bindings/gpio/
Dnxp,pca95xx.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: PCA95xx series I2C-based GPIO expander
8 include: [gpio-controller.yaml, i2c-device.yaml]
11 has-pud:
13 description: Supports pull-up/pull-down
15 has-interrupt-mask-reg:
17 description: Has Interrupt mask register (PCAL95xx)
19 interrupt-gpios:
20 type: phandle-array
21 description: Interrupt GPIO pin (active-low open-drain)
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit82xx2.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 compatible = "mmio-sram";
13 reg = <0x80100000 DT_SIZE_K(256)>;
16 intc: interrupt-controller@f03f00 {
17 compatible = "ite,it8xxx2-intc-v2";
18 #address-cells = <0>;
19 #interrupt-cells = <2>;
20 interrupt-controller;
21 reg = <0x00f03f00 0x0100>;
25 compatible = "ite,it8xxx2-watchdog";
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/Zephyr-latest/tests/drivers/gpio/gpio_ite_it8xxx2_v2/boards/
Dnative_sim.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/gpio/gpio.h>
8 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
12 intc: interrupt-controller@f03f00 {
14 #address-cells = <0>;
15 #interrupt-cells = <2>;
16 interrupt-controller;
17 reg = <0x00f03f00 0x0100>;
21 compatible = "ite,it8xxx2-gpio-v2";
22 reg = <0x00f01601 1 /* GPDR (set) */
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_intel.c2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 ((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
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Dgpio_pca95xx.c6 * SPDX-License-Identifier: Apache-2.0
12 * @file Driver for PCA95XX and PCAL95XX I2C-based GPIO driver.
98 /* Self-reference to the driver instance */
104 /* interrupt triggering pin masks */
120 static int read_port_reg(const struct device *dev, uint8_t reg, uint8_t pin, in read_port_reg() argument
123 const struct gpio_pca95xx_config * const config = dev->config; in read_port_reg()
128 reg++; in read_port_reg()
131 ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf); in read_port_reg()
134 config->bus.addr, reg, ret); in read_port_reg()
146 LOG_DBG("PCA95XX[0x%X]: Read: REG[0x%X] = 0x%X", in read_port_reg()
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Dgpio_tca6424a.c4 * SPDX-License-Identifier: Apache-2.0
63 * @param reg Address of the first of 3 registers to be read.
70 static int read_port_regs(const struct device *dev, uint8_t reg, uint32_t *buf) in read_port_regs() argument
72 const struct tca6424a_drv_cfg *const config = dev->config; in read_port_regs()
76 ret = i2c_burst_read_dt(&config->i2c_spec, reg, (uint8_t *)&port_data, 3); in read_port_regs()
78 LOG_ERR("%s: error reading register 0x%X (%d)", dev->name, in read_port_regs()
79 reg, ret); in read_port_regs()
85 LOG_DBG("%s: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X, " in read_port_regs()
86 "REG[0x%X] = 0x%X", in read_port_regs()
87 dev->name, reg, (*buf & 0xFF), (reg + 1), ((*buf >> 8) & 0xFF), in read_port_regs()
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Dgpio_rt1718s_port.c4 * SPDX-License-Identifier: Apache-2.0
41 const struct gpio_rt1718s_port_config *const config = dev->config; in gpio_rt1718s_pin_config()
42 struct gpio_rt1718s_port_data *const data = dev->data; in gpio_rt1718s_pin_config()
48 return -ENOTSUP; in gpio_rt1718s_pin_config()
53 return -ENOTSUP; in gpio_rt1718s_pin_config()
56 /* RT1718S has 3 GPIOs so check range */ in gpio_rt1718s_pin_config()
58 return -EINVAL; in gpio_rt1718s_pin_config()
64 /* Set pull-high/low input */ in gpio_rt1718s_pin_config()
75 /* Set push-pull or open-drain */ in gpio_rt1718s_pin_config()
86 k_sem_take(&data->lock, K_FOREVER); in gpio_rt1718s_pin_config()
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Dgpio_mcp23xxx.c5 * SPDX-License-Identifier: Apache-2.0
9 * @file Driver for MPC23xxx I2C/SPI-based GPIO driver.
35 * @param reg The register to be read.
40 static int read_port_regs(const struct device *dev, uint8_t reg, uint16_t *buf) in read_port_regs() argument
42 const struct mcp23xxx_config *config = dev->config; in read_port_regs()
44 if (config->ngpios == 16U) { in read_port_regs()
45 reg *= 2; in read_port_regs()
48 return config->read_fn(dev, reg, buf); in read_port_regs()
58 * @param reg Register to be written.
63 static int write_port_regs(const struct device *dev, uint8_t reg, uint16_t value) in write_port_regs() argument
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Dgpio_pca_series.c4 * SPDX-License-Identifier: Apache-2.0
8 * @file Driver for PCA(L)xxxx SERIES I2C-based GPIO expander.
69 * Device reg layout types:
70 * - Type 0: PCA953X, PCA955X
71 * - Type 1: PCAL953X, PCAL955X, PCAL64XXA
72 * - Type 2: PCA957X
73 * - Type 3: PCAL65XX
103 * port-level "pin output configuration" register.
132 * @brief interrupt config for interrupt_edge register
144 uint8_t port_no; /* number of 8-pin ports on device */
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c5 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
34 * deal with (one configuration byte per interrupt). PENDBASE has to
50 return gic_rdists[arch_curr_cpu()->id]; in gic_get_rdist()
80 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_setup()
95 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_set_priority()
107 uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192]; in arm_gic_lpi_is_enabled()
136 uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1)); in arm_gic_irq_set_priority() local
142 /* Disable the interrupt */ in arm_gic_irq_set_priority()
143 sys_write32(mask, ICENABLER(base, idx)); in arm_gic_irq_set_priority()
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Dintc_ioapic_priv.h1 /* ioapic_priv.h - private IOAPIC APIs */
4 * Copyright (c) 2012-2015 Wind River Systems, Inc.
7 * SPDX-License-Identifier: Apache-2.0
16 #define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
28 /* Interrupt delivery type */
35 #define IOAPIC_MRE_MASK 0x00ff0000 /* Max Red. entry mask */
37 #define IOAPIC_PRQ 0x00008000 /* this has IRQ reg */
Dintc_plic.c2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
12 * @brief Platform Level Interrupt Controller (PLIC) driver
13 * for RISC-V processors
34 * https://github.com/riscv/riscv-plic-spec
54 /* PLIC registers are 32-bit memory-mapped */
82 mem_addr_t reg; member
133 const struct plic_config *config = dev->config; in get_plic_enabled_size()
135 return local_irq_to_reg_index(config->nr_irqs) + 1; in get_plic_enabled_size()
140 const struct plic_config *config = dev->config; in get_hart_context()
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/Zephyr-latest/dts/bindings/misc/
Dnxp,s32-emios.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-emios"
15 reg:
21 interrupt-names:
27 clock-divider:
33 internal-cnt:
37 A mask for channels that have internal counter, lsb is channel 0.
39 child-binding:
40 child-binding:
42 Node for eMIOS master bus. Each channel is capable to become a master bus has
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/Zephyr-latest/drivers/usb_c/tcpc/
Dtcpci.c3 * SPDX-License-Identifier: Apache-2.0
212 int tcpci_read_reg8(const struct i2c_dt_spec *i2c, uint8_t reg, uint8_t *value) in tcpci_read_reg8() argument
217 ret = i2c_write_read(i2c->bus, i2c->addr, &reg, sizeof(reg), value, sizeof(*value)); in tcpci_read_reg8()
225 LOG_ERR(LOG_COMM_ERR_STR, i2c->bus->name, i2c->addr, "r8", reg, *value); in tcpci_read_reg8()
231 int tcpci_write_reg8(const struct i2c_dt_spec *i2c, uint8_t reg, uint8_t value) in tcpci_write_reg8() argument
233 uint8_t buf[2] = {reg, value}; in tcpci_write_reg8()
237 ret = i2c_write(i2c->bus, buf, 2, i2c->addr); in tcpci_write_reg8()
245 LOG_ERR(LOG_COMM_ERR_STR, i2c->bus->name, i2c->addr, "w8", reg, value); in tcpci_write_reg8()
251 int tcpci_update_reg8(const struct i2c_dt_spec *i2c, uint8_t reg, uint8_t mask, uint8_t value) in tcpci_update_reg8() argument
256 ret = tcpci_read_reg8(i2c, reg, &old_value); in tcpci_update_reg8()
[all …]
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_nxp_lcdic.c4 * SPDX-License-Identifier: Apache-2.0
66 /* Enable command done interrupt */
153 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_reset_state()
154 LCDIC_Type *base = config->base; in mipi_dbi_lcdic_reset_state()
156 base->CTRL &= ~LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
158 base->CTRL |= LCDIC_CTRL_LCDIC_EN_MASK; in mipi_dbi_lcdic_reset_state()
168 const struct mipi_dbi_lcdic_config *config = dev->config; in mipi_dbi_lcdic_start_dma()
169 struct mipi_dbi_lcdic_data *data = dev->data; in mipi_dbi_lcdic_start_dma()
170 struct stream *stream = &data->dma_stream; in mipi_dbi_lcdic_start_dma()
171 uint32_t aligned_len = data->cmd_bytes & (~0x3); in mipi_dbi_lcdic_start_dma()
[all …]
/Zephyr-latest/drivers/sensor/bosch/bmi08x/
Dbmi08x.h5 * SPDX-License-Identifier: Apache-2.0
53 /* Accel Interrupt status0 register */
56 /* Accel Interrupt status1 register */
80 /* Accel Interrupt pin 1 configuration register */
83 /* Accel Interrupt pin 2 configuration register */
86 /* Accel Interrupt latch configuration register */
89 /* Accel Interrupt pin1 mapping register */
92 /* Accel Interrupt pin2 mapping register */
95 /* Accel Interrupt map register */
124 /* Interrupt masks */
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/Zephyr-latest/drivers/rtc/
Drtc_pcf8563.c4 * SPDX-License-Identifier: Apache-2.0
29 * include all the interrupt code if the user configured it in the dts
43 * https://www.nxp.com/docs/en/data-sheet/PCF8563.pdf
91 * https://www.nxp.com/docs/en/data-sheet/PCF8563.pdf page 10 starting
100 * byte is 0 (ignored bit) 100 (the 4) 0011 (the 3) -> 0100001
103 * the datasheet because they may contain unexpected values. Applying a mask will help us
108 const struct pcf8563_config *config = dev->config; in pcf8563_set_time()
114 return -EINVAL; in pcf8563_set_time()
118 raw_time[0] = bin2bcd(timeptr->tm_sec); in pcf8563_set_time()
121 raw_time[1] = bin2bcd(timeptr->tm_min); in pcf8563_set_time()
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/Zephyr-latest/dts/xtensa/intel/
Dintel_adsp_cavs25_tgph.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx6";
18 reg = <0>;
19 cpu-power-states = <&d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx6";
27 reg = <1>;
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Dintel_adsp_cavs25.dtsi4 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "cdns,tensilica-xtensa-lx6";
18 reg = <0>;
19 cpu-power-states = <&d3>;
20 i-cache-line-size = <64>;
21 d-cache-line-size = <64>;
26 compatible = "cdns,tensilica-xtensa-lx6";
27 reg = <1>;
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/Zephyr-latest/scripts/dts/python-devicetree/tests/
Dtest.dts4 * SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
16 interrupt-parent-test {
18 compatible = "interrupt-three-cell";
19 #interrupt-cells = <3>;
20 interrupt-controller;
24 interrupt-names = "foo", "bar";
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
28 interrupts-extended-test {
29 controller-0 {
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/Zephyr-latest/drivers/spi/
Dspi_pl022.c4 * SPDX-License-Identifier: Apache-2.0
130 * Interrupt Mask Set/Clear Register
141 /* Receive Overrun Interrupt mask */
143 /* Receive timeout Interrupt mask */
145 /* Receive FIFO Interrupt mask */
147 /* Transmit FIFO Interrupt mask */
151 * Raw Interrupt Status Register
162 /* Receive Overrun Raw Interrupt status */
164 /* Receive Timeout Raw Interrupt status */
166 /* Receive FIFO Raw Interrupt status */
[all …]
/Zephyr-latest/drivers/i3c/
Di3c_mcux.c6 * SPDX-License-Identifier: Apache-2.0
84 /** Interrupt configuration function. */
129 * @param reg Pointer to 32-bit Register.
130 * @param mask Mask to the register value.
135 * @retval -ETIMEDOUT Timedout without matching.
137 static int reg32_poll_timeout(volatile uint32_t *reg, in reg32_poll_timeout() argument
138 uint32_t mask, uint32_t match, in reg32_poll_timeout() argument
143 * quickly (some sub-microseconds) so no extra in reg32_poll_timeout()
146 if (!WAIT_FOR((sys_read32((mm_reg_t)reg) & mask) == match, timeout_us, /*nop*/)) { in reg32_poll_timeout()
147 return -ETIMEDOUT; in reg32_poll_timeout()
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/Zephyr-latest/include/zephyr/drivers/usb_c/
Dusbc_tcpc.h3 * SPDX-License-Identifier: Apache-2.0
8 * @brief USBC Type-C Port Controller device APIs
10 * This file contains the USB Type-C Port Controller device APIs.
11 * All Type-C Port Controller device drivers should implement the
19 * @brief USB Type-C Port Controller API
20 * @defgroup usb_type_c_port_controller_api USB Type-C Port Controller API
59 /** A high-voltage alarm has occurred */
61 /** A low-voltage alarm has occurred */
63 /** A fault has occurred. Read the FAULT_STATUS register */
65 /** TCPC RX buffer has overflowed */
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/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483.c3 * SPDX-License-Identifier: Apache-2.0
21 "Switch Status ", "Interrupt 1 ", "Interrupt 2 ",
22 "Interrupt 1 Mask ", "Interrupt 2 Mask ", "OVLO Threshold ",
32 /** GPIO used as interrupt request */
37 /** Boolean value whether to use high-voltage source if true or 5V source if false */
48 /** Interrupt request callback object */
61 static int read_reg(const struct device *dev, uint8_t reg, uint8_t *value) in read_reg() argument
63 const struct nx20p3483_cfg *cfg = dev->config; in read_reg()
66 ret = i2c_reg_read_byte(cfg->bus.bus, cfg->bus.addr, reg, value); in read_reg()
68 LOG_ERR("Error reading reg %02x: %d", reg, ret); in read_reg()
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/Zephyr-latest/drivers/ethernet/phy/
Dphy_adin2111.c5 * SPDX-License-Identifier: Apache-2.0
48 /* System Interrupt Mask Register */
50 /* System Interrupt Status Register */
53 * Mask of reserved interrupts that indicates a fatal error in the system.
56 * - RM mask 0x6FFF
57 * - ADI driver example mask 0x2BFF
66 /* PHY Subsystem Interrupt Mask Register */
68 /* PHY Subsystem Interrupt Status Register */
73 /* Software Power-down Control Register */
77 /* Software Power-down Status */
[all …]

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