5  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
34  * deal with (one configuration byte per interrupt). PENDBASE has to
50 	return gic_rdists[arch_curr_cpu()->id];  in gic_get_rdist()
80 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_setup()
95 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_set_priority()
107 	uint8_t *cfg = &((uint8_t *)lpi_prop_table)[intid - 8192];  in arm_gic_lpi_is_enabled()
136 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_priority()  local
142 	/* Disable the interrupt */  in arm_gic_irq_set_priority()
143 	sys_write32(mask, ICENABLER(base, idx));  in arm_gic_irq_set_priority()
149 	/* Interrupt type config */  in arm_gic_irq_set_priority()
152 		shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;  in arm_gic_irq_set_priority()
171 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_enable()  local
176 	 * Affinity routing is enabled for Armv8-A Non-secure state (GICD_CTLR.ARE_NS  in arm_gic_irq_enable()
185 	sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_enable()
196 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_disable()  local
199 	sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));  in arm_gic_irq_disable()
211 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_enabled()  local
217 	return (val & mask) != 0;  in arm_gic_irq_is_enabled()
222 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_is_pending()  local
228 	return (val & mask) != 0;  in arm_gic_irq_is_pending()
233 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_set_pending()  local
236 	sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_set_pending()
241 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));  in arm_gic_irq_clear_pending()  local
244 	sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));  in arm_gic_irq_clear_pending()
251 	/* (Pending -> Active / AP) or (AP -> AP) */  in arm_gic_get_active()
260 	 * Interrupt request deassertion from peripheral to GIC happens  in arm_gic_eoi()
261 	 * by clearing interrupt condition by a write to the peripheral  in arm_gic_eoi()
272 	/* (AP -> Pending) Or (Active -> Inactive) or (AP to AP) nested case */  in arm_gic_eoi()
332  * LPI configuration is global, each redistributor has a pending table
339 	uint64_t reg;  in gicv3_rdist_setup_lpis()  local
356 	reg = (GIC_BASER_SHARE_INNER << GITR_PROPBASER_SHAREABILITY_SHIFT) |  in gicv3_rdist_setup_lpis()
360 	      ((lpi_id_bits - 1) & GITR_PROPBASER_ID_BITS_MASK);  in gicv3_rdist_setup_lpis()
361 	sys_write64(reg, rdist + GICR_PROPBASER);  in gicv3_rdist_setup_lpis()
365 	reg = (GIC_BASER_SHARE_INNER << GITR_PENDBASER_SHAREABILITY_SHIFT) |  in gicv3_rdist_setup_lpis()
370 	sys_write64(reg, rdist + GICR_PENDBASER);  in gicv3_rdist_setup_lpis()
393 	/* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */  in gicv3_cpuif_init()
453 	 * but GIC distributor should avoid to be re-configured in order to avoid crash the  in gicv3_dist_init()
454 	 * OSes has already been started.  in gicv3_dist_init()
485 		/* Disable interrupt */  in gicv3_dist_init()
519 	 * means the GIC is under single security state which has only two  in gicv3_dist_init()
522 	 * interrupt.  in gicv3_dist_init()
556 	uint64_t mask = BIT64_MASK(8);  in arm_gic_aff_matching()  local
558 	return (gicr_aff & mask) == (aff & mask);  in arm_gic_aff_matching()
605 	cpu = arch_curr_cpu()->id;  in __arm_gic_init()