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/Zephyr-latest/dts/x86/intel/
Dgpio_common.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
8 #include <zephyr/dt-bindings/acpi/acpi.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
14 compatible = "intel,gpio";
15 interrupt-parent = <&intc>;
17 gpio-controller;
18 #gpio-cells = <2>;
23 compatible = "intel,gpio";
24 interrupt-parent = <&intc>;
[all …]
/Zephyr-latest/dts/bindings/gpio/
Dnxp,s32-gpio.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 NXP S32 GPIO controller.
7 The GPIO controller provides the option to route external input pad interrupts
8 to either the SIUL2 EIRQ interrupt controller or, when available on the SoC,
9 the WKPU interrupt controller. By default, GPIO interrupts are routed to the
10 SIUL2 EIRQ interrupt controller.
12 To route external interrupts to the WKPU interrupt controller, the GPIO
14 the following snippet of devicetree source code instructs the GPIO controller
15 to route the interrupt from pin 9 of `gpioa` to the WKPU interrupt controller:
[all …]
Dbrcm,iproc-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Broadcom iProc GPIO Controller
6 compatible: "brcm,iproc-gpio"
8 include: [gpio-controller.yaml, base.yaml]
15 GPIO/PINCONF controller registers
19 description: Total number of in-use slots in GPIO controller
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
Dawinic,aw9523b-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: AW9523B GPIO Controller
6 compatible: "awinic,aw9523b-gpio"
8 include: gpio-controller.yaml
10 on-bus: aw9523b
13 int-gpios:
14 type: phandle-array
16 Set GPIO connected to the controller INTN pin.
19 reset-gpios:
20 type: phandle-array
[all …]
Dgpio-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for GPIO controllers
7 "gpio-controller":
10 description: Convey's this node is a GPIO controller
11 "#gpio-cells":
14 description: Number of items to expect in a GPIO specifier
19 This property indicates the number of in-use slots of available slots
28 gpio-reserved-ranges:
31 If not all the GPIOs at offsets 0...N-1 are usable for ngpios = <N>, then
36 For example, setting "gpio-reserved-ranges = <3 2>, <10 1>;" means that
[all …]
Dnxp,lpc11u6x-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP LPC11U6X GPIO node
6 compatible: "nxp,lpc11u6x-gpio"
8 include: [gpio-controller.yaml, base.yaml]
17 "#gpio-cells":
23 description: index of the first GPIO for this port.
33 controller associated with the GPIO controller.
35 gpio-cells:
36 - pin
37 - flags
/Zephyr-latest/tests/drivers/build_all/gpio/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * with real-world devicetree nodes, to allow these tests to run on
15 #address-cells = <1>;
16 #size-cells = <1>;
18 test_gpio: gpio@deadbeef {
19 compatible = "vnd,gpio";
20 gpio-controller;
22 #gpio-cells = <0x2>;
26 test_gpio_dw: gpio@c0ffee {
27 compatible = "snps,designware-gpio";
[all …]
/Zephyr-latest/dts/arm/renesas/rz/rzg/
Dr9a08g045.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m33";
23 clock-frequency = <250000000>;
24 #address-cells = <1>;
25 #size-cells = <1>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defm32hg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv6-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
10 zephyr,flash-controller = &msc;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-m0+";
24 compatible = "mmio-sram";
28 msc: flash-controller@400c0000 {
[all …]
Defr32fg1p.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/pwm/pwm.h>
11 zephyr,flash-controller = &msc;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-m4f";
25 compatible = "mmio-sram";
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Defm32_pg_1b.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
14 zephyr,flash-controller = &msc;
18 #address-cells = <1>;
19 #size-cells = <0>;
24 compatible = "mmio-sram";
28 msc: flash-controller@400e0000 {
29 compatible = "silabs,gecko-flash-controller";
[all …]
Defm32_jg_pg_12b.dtsi4 * Copyright (c) 2021 T-Mobile USA, Inc.
6 * SPDX-License-Identifier: Apache-2.0
9 #include <arm/armv7-m.dtsi>
10 #include <zephyr/dt-bindings/adc/adc.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
19 zephyr,flash-controller = &msc;
23 #address-cells = <1>;
24 #size-cells = <0>;
[all …]
Defr32mg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
7 #include <zephyr/dt-bindings/pwm/pwm.h>
12 zephyr,flash-controller = &msc;
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m4f";
26 compatible = "mmio-sram";
[all …]
Defm32wg.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
4 #include <zephyr/dt-bindings/gpio/gpio.h>
5 #include <zephyr/dt-bindings/i2c/i2c.h>
10 zephyr,flash-controller = &msc;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
24 compatible = "mmio-sram";
28 msc: flash-controller@400c0000 {
[all …]
Defr32xg13p.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
14 zephyr,flash-controller = &msc;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-m4f";
28 compatible = "mmio-sram";
32 msc: flash-controller@400e0000 {
[all …]
Defm32gg11b.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
16 zephyr,flash-controller = &msc;
20 #address-cells = <1>;
21 #size-cells = <0>;
24 compatible = "arm,cortex-m4f";
30 compatible = "mmio-sram";
34 msc: flash-controller@40000000 {
[all …]
/Zephyr-latest/tests/drivers/gpio/gpio_reserved_ranges/boards/
Dnative_posix.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-reserved-ranges";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 test_gpio_1: gpio@deadbeef {
15 compatible = "vnd,gpio-device";
16 gpio-controller;
18 #gpio-cells = < 0x2 >;
21 gpio-reserved-ranges = <0 4>, <5 3>, <9 5>, <11 2>,
26 test_gpio_2: gpio@abcd1234 {
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_04/
Dpsoc6_04.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-latest/dts/arm/ti/
Dlm3s6965.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <arm/armv7-m.dtsi>
7 #address-cells = <1>;
8 #size-cells = <0>;
12 compatible = "arm,cortex-m3";
18 compatible = "mmio-sram";
22 sysclk: system-clock {
23 compatible = "fixed-clock";
24 clock-frequency = <12000000>;
25 #clock-cells = <0>;
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/psoc6_03/
Dpsoc6_03.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "arm,cortex-m0+";
22 compatible = "arm,cortex-m4f";
27 flash-controller@40240000 {
28 compatible = "infineon,cat1-flash-controller";
30 #address-cells = <1>;
31 #size-cells = <1>;
34 compatible = "soc-nv-flash";
[all …]
/Zephyr-latest/dts/arm/gd/gd32l23x/
Dgd32l23x.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv8-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/clock/gd32l23x-clocks.h>
12 #include <zephyr/dt-bindings/reset/gd32l23x.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m23";
22 clock-frequency = <DT_FREQ_M(64)>;
[all …]
/Zephyr-latest/dts/arm/renesas/rcar/gen4/
Dr8a779f0.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
13 /* The last four registers of this controller are
17 pfc: pin-controller@e6050000 {
18 compatible = "renesas,rcar-pfc";
25 /* Clock controller
28 cpg: clock-controller@e6150000 {
29 compatible = "renesas,r8a779f0-cpg-mssr";
31 #clock-cells = <2>;
[all …]
/Zephyr-latest/dts/arm/gd/gd32f3x0/
Dgd32f3x0.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/adc/gd32f3x0.h>
12 #include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
13 #include <zephyr/dt-bindings/reset/gd32f3x0.h>
17 #address-cells = <1>;
18 #size-cells = <0>;
21 clock-frequency = <DT_FREQ_M(108)>;
[all …]
/Zephyr-latest/dts/arm/nuvoton/
Dm48x.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <0>;
18 compatible = "arm,cortex-m4f";
24 compatible = "mmio-sram";
28 compatible = "serial-flash";
29 erase-block-size = <4096>;
30 write-block-size = <1>;
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_xlnx_ps.c2 * Xilinx Processor System MIO / EMIO GPIO controller driver
6 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
23 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
24 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_dev_data *const)(_dev)->data)
30 static DEVICE_API(gpio, gpio_xlnx_ps_default_apis);
33 * @brief Initialize a Xilinx PS GPIO controller parent device
35 * Initialize a Xilinx PS GPIO controller parent device, whose task it is
36 * to handle the IRQ line of each controller instance, while the configuration,
[all …]

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