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Searched +full:girq +full:- +full:cells (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/dts/bindings/dma/
Dmicrochip,xec-dmac.yaml3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
24 aggregated-girq:
28 provide the handle to the GIRQ.
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
55 # dma-names = "rx", "tx";
61 dma-cells:
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/Zephyr-latest/dts/arm/microchip/
Dmec172x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "microchip,xec-pcr";
13 reg-names = "pcrr", "vbatr";
15 core-clock-div = <1>;
17 pll-32k-src = <MCHP_XEC_PLL_CLK32K_SRC_SIL_OSC>;
18 periph-32k-src = <MCHP_XEC_PERIPH_CLK32K_SRC_SO_SO>;
19 clk32kmon-period-min = <1435>;
20 clk32kmon-period-max = <1495>;
21 clk32kmon-duty-cycle-var-max = <132>;
22 clk32kmon-valid-min = <4>;
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Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
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/Zephyr-latest/dts/bindings/gpio/
Dmicrochip,xec-gpio.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
Dmicrochip,xec-gpio-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-gpio-v2"
8 include: [gpio-controller.yaml, base.yaml]
14 port-id:
19 girq-id:
22 description: Aggregated GIRQ number for this bank of 32 GPIO pins.
24 "#gpio-cells":
27 gpio-cells:
28 - pin
29 - flags
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-saf-v2.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-espi-saf-v2"
9 include: espi-controller.yaml
26 poll-timeout:
30 poll-interval:
34 consec-rd-timeout:
38 sus-chk-delay:
42 sus-rsm-interval:
46 "#girq-cells":
50 "#pcr-cells":
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Dmicrochip,xec-espi-host-dev.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-espi-host-dev"
10 on-bus: espi
23 description: array of GIRQ and bit positions
30 host-io:
37 host-io-addr-mask:
44 host-mem:
51 emi-mems:
61 "emi-mem-cells":
65 emi-mem-cells:
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/Zephyr-latest/dts/bindings/tach/
Dmicrochip,xec-tach.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-tach"
8 include: [tach.yaml, pinctrl-device.yaml]
11 "#address-cells":
14 "#size-cells":
27 Array of GIRQ and bit position pairs for each interrupt
/Zephyr-latest/dts/bindings/input/
Dmicrochip,xec-kbd.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-kbd"
9 include: [kbd-matrix-common.yaml, pinctrl-device.yaml]
12 "#address-cells":
16 "#size-cells":
29 description: Array of pairs of GIRQ number and bit position
36 row-size:
39 col-size:
/Zephyr-latest/dts/bindings/adc/
Dmicrochip,xec-adc.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-adc"
9 include: [adc-controller.yaml, pinctrl-device.yaml]
18 "#io-channel-cells":
24 description: Array of pairs of GIRQ number and bit position
41 pinctrl-0:
44 pinctrl-names:
47 io-channel-cells:
48 - input
/Zephyr-latest/dts/bindings/pwm/
Dmicrochip,xec-pwmbbled.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-pwmbbled"
20 description: Array of pairs of GIRQ number and bit position
27 clock-select:
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
35 - "PWM_BBLED_CLK_32K"
36 - "PWM_BBLED_CLK_48M"
38 pinctrl-0:
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/Zephyr-latest/doc/releases/
Drelease-notes-2.7.rst17 * Support for M-Profile Vector Extensions (MVE) on ARMv8.1-M
18 * Improved thread safety for Newlib and C++ on SMP-capable systems
20 * New Action-based Power Management API
23 * Linker Support for Tightly-Coupled Memory in RISC-V
25 * Support for extended PCI / PCIe capabilities, improved MIS-X support
33 * The kernel now supports both 32- and 64-bit architectures
36 * We added support for Point-to-Point Protocol (PPP)
37 * We added support for UpdateHub, an end-to-end solution for over-the-air device updates
38 * We added support for ARM Cortex-R Architecture
40 * Expanded support for ARMv6-M architecture
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