Home
last modified time | relevance | path

Searched +full:girq +full:- +full:bit (Results 1 – 25 of 50) sorted by relevance

12

/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_mchp_xec_ecia.h4 * SPDX-License-Identifier: Apache-2.0
11 * Reference Manuals for MEC152x and MEC172x ARM(r) 32-bit MCUs
26 * @param girq_id is the GIRQ number (8 - 26)
27 * @param src is the interrupt source in the GIRQ (0 - 31)
35 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
42 * @param girq_id is the GIRQ number (8 - 26)
43 * @param src is the interrupt source in the GIRQ (0 - 31)
51 * @param ecia_info is GIRQ connection encoded with MCHP_XEC_ECIA
56 /* callback for ECIA GIRQ interrupt source */
62 * @param girq_id is the GIRQ number (8 - 26)
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_mchp_ecia_xec.c4 * SPDX-License-Identifier: Apache-2.0
22 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
72 ((const struct xec_ecia_config *const)(ecia_dev)->config)
75 ((const struct xec_girq_config *const)(girq_dev)->config)
78 ((struct xec_girq_src_data *const)(girq_dev)->data)
81 * Enable/disable specified GIRQ's aggregated output. Aggregated output is the
82 * bit-wise or of all the GIRQ's result bits.
89 regs->BLK_EN_SET = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
91 regs->BLK_EN_CLR = BIT(girq_num); in mchp_xec_ecia_girq_aggr_en()
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
/Zephyr-latest/dts/bindings/i2c/
Dmicrochip,xec-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-i2c"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
19 girq:
22 description: GIRQ for this device
24 girq-bit:
27 description: Bit position in GIRQ for this device
32 description: PCR sleep register index and bit position
34 pinctrl-0:
37 pinctrl-names:
[all …]
Dmicrochip,xec-i2c-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-i2c-v2"
8 include: [i2c-controller.yaml, pinctrl-device.yaml]
22 description: array of GIRQ numbers [8:26] and bit positions [0:31]
27 description: PCR sleep register index and bit position
29 pinctrl-0:
32 pinctrl-names:
/Zephyr-latest/dts/bindings/interrupt-controller/
Dmicrochip,xec-ecia-girq.yaml1 description: Microchip XEC series External Interrupt Aggregator GIRQ
3 compatible: "microchip,xec-ecia-girq"
14 girq-id:
17 description: GIRQ ID number [0, 18]
23 Bit positions of each source implemented by this GIRQ.
/Zephyr-latest/drivers/timer/
Dmchp_xec_rtos_timer.c4 * SPDX-License-Identifier: Apache-2.0
67 * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
68 * CLK_REQ, or RST_EN registers. Property at index 1 is the bit position.
77 /* Mask off bits[31:28] of 32-bit count */
109 * MEC GIRQ numbers are documented as 8 to 26, check and convert to zero
112 static inline void girq_src_clr(int girq, int bitpos) in girq_src_clr() argument
114 if ((girq < 8) || (girq > 26)) { in girq_src_clr()
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()
121 static inline void girq_src_en(int girq, int bitpos) in girq_src_en() argument
123 if ((girq < 8) || (girq > 26)) { in girq_src_en()
[all …]
/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi-ldma.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-qmspi-ldma"
9 include: [spi-controller.yaml, pinctrl-device.yaml]
26 This information includes the aggregated GIRQ number, GIRQ bit
27 position, aggregated GIRQ NVIC connection, and direct NVIC
28 connection of the GIRQ bit.
30 pinctrl-0:
33 pinctrl-names:
39 QMSPI data lines 1, 2, or 4. 1 data line is full-duplex
40 MOSI and MISO or half-duplex on MOSI only. Lines set to 2
[all …]
/Zephyr-latest/drivers/espi/
Despi_mchp_xec_v2.h4 * SPDX-License-Identifier: Apache-2.0
27 void (*the_isr)(int girq, int bpos, void *dev);
31 uint8_t gid; /* GIRQ id [8, 26] */
32 uint8_t gpos; /* bit position in GIRQ [0, 31] */
33 uint8_t anid; /* Aggregated GIRQ NVIC number */
34 uint8_t dnid; /* Direct GIRQ NVIC number */
49 ((struct espi_xec_config * const)(dev)->config)
62 ((struct espi_xec_data * const)(dev)->data)
66 uint8_t bit; member
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h4 * SPDX-License-Identifier: Apache-2.0
10 * Encode peripheral interrupt information into a 32-bit unsigned.
11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
13 * na = bits[23:16], aggregated GIRQ NVIC number
/Zephyr-latest/dts/bindings/dma/
Dmicrochip,xec-dmac.yaml3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
17 description: PCR register index and bit position
24 aggregated-girq:
28 provide the handle to the GIRQ.
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
55 # dma-names = "rx", "tx";
[all …]
/Zephyr-latest/drivers/input/
Dinput_xec_kbd.c4 * SPDX-License-Identifier: Apache-2.0
33 uint8_t girq; member
49 struct xec_kbd_config const *cfg = dev->config; in xec_kbd_clear_girq_status()
52 mchp_xec_ecia_girq_src_clr(cfg->girq, cfg->girq_pos); in xec_kbd_clear_girq_status()
54 MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos); in xec_kbd_clear_girq_status()
60 struct xec_kbd_config const *cfg = dev->config; in xec_kbd_configure_girq()
63 mchp_xec_ecia_enable(cfg->girq, cfg->girq_pos); in xec_kbd_configure_girq()
65 MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos); in xec_kbd_configure_girq()
72 struct xec_kbd_config const *cfg = dev->config; in xec_kbd_clr_slp_en()
74 z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0); in xec_kbd_clr_slp_en()
[all …]
/Zephyr-latest/dts/bindings/led/
Dmicrochip,xec-bbled.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: [base.yaml, pinctrl-device.yaml]
8 compatible: "microchip,xec-bbled"
20 description: Array of pairs of GIRQ number and bit position
25 description: BBLED PCR register index and bit position
/Zephyr-latest/dts/bindings/peci/
Dmicrochip,xec-peci.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-peci"
8 include: [peci.yaml, pinctrl-device.yaml]
20 description: Array of pairs of GIRQ number and bit position
25 description: ADC PCR register index and bit position
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-saf-v2.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-espi-saf-v2"
9 include: espi-controller.yaml
24 description: Array of eSPI PCR register index and bit position
26 poll-timeout:
30 poll-interval:
34 consec-rd-timeout:
38 sus-chk-delay:
42 sus-rsm-interval:
46 "#girq-cells":
[all …]
/Zephyr-latest/dts/bindings/mtd/
Dmicrochip,xec-eeprom.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Microchip on-chip EEPROM
6 compatible: "microchip,xec-eeprom"
8 include: [eeprom-base.yaml, pinctrl-device.yaml]
18 Array of GIRQ and bit position pairs for each interrupt
24 description: PS2 PCR register index and bit position
/Zephyr-latest/dts/bindings/watchdog/
Dmicrochip,xec-watchdog.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "microchip,xec-watchdog"
20 description: Array of GIRQ numbers [8:26] and bit positions [0:31].
25 description: PCR sleep enable register index and bit position.
/Zephyr-latest/dts/bindings/serial/
Dmicrochip,xec-uart.yaml3 compatible: "microchip,xec-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
22 description: UART GIRQ and bit position in EC interrupt aggregator
27 description: UART Power Clock Reset(PCR) register index and bit position
29 pinctrl-0:
32 pinctrl-names:
35 wakerx-gpios:
36 type: phandle-array
/Zephyr-latest/dts/bindings/tach/
Dmicrochip,xec-tach.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-tach"
8 include: [tach.yaml, pinctrl-device.yaml]
11 "#address-cells":
14 "#size-cells":
27 Array of GIRQ and bit position pairs for each interrupt
33 description: PCR sleep register index and bit position
/Zephyr-latest/dts/bindings/ps2/
Dmicrochip,xec-ps2.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-ps2"
8 include: [ps2.yaml, pinctrl-device.yaml]
21 Array of GIRQ and bit position pairs for each interrupt
27 description: PS2 PCR register index and bit position
29 wakerx-gpios:
30 type: phandle-array
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-m4";
[all …]
/Zephyr-latest/dts/bindings/crypto/
Dmicrochip,xec-symcr.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-symcr"
20 description: XEC ECIA GIRQ number and bit position.
/Zephyr-latest/dts/bindings/rtc/
Dmicrochip,xec-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-timer"
17 clock-frequency:
23 description: Timer frequency equals clock-frequency divided by the prescaler value
25 max-value:
33 description: Array of GIRQ numbers [8:26] and bit positions [0:31].
38 description: PCR sleep enable register index and bit position.
/Zephyr-latest/dts/bindings/input/
Dmicrochip,xec-kbd.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "microchip,xec-kbd"
9 include: [kbd-matrix-common.yaml, pinctrl-device.yaml]
12 "#address-cells":
16 "#size-cells":
29 description: Array of pairs of GIRQ number and bit position
34 description: ADC PCR register index and bit position
36 row-size:
39 col-size:
/Zephyr-latest/dts/bindings/timer/
Dmicrochip,xec-rtos-timer.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-rtos-timer"
20 description: Array of GIRQ numbers [8:26] and bit positions [0:31].

12