4  * SPDX-License-Identifier: Apache-2.0
67  * pcrs property at index 0 is register index into array of 32-bit PCR SLP_EN,
68  * CLK_REQ, or RST_EN registers. Property at index 1 is the bit position.
77 /* Mask off bits[31:28] of 32-bit count */
109  * MEC GIRQ numbers are documented as 8 to 26, check and convert to zero
112 static inline void girq_src_clr(int girq, int bitpos)  in girq_src_clr()  argument
114 	if ((girq < 8) || (girq > 26)) {  in girq_src_clr()
118 	ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos);  in girq_src_clr()
121 static inline void girq_src_en(int girq, int bitpos)  in girq_src_en()  argument
123 	if ((girq < 8) || (girq > 26)) {  in girq_src_en()
127 	ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos);  in girq_src_en()
130 static inline void girq_src_dis(int girq, int bitpos)  in girq_src_dis()  argument
132 	if ((girq < 8) || (girq > 26)) {  in girq_src_dis()
136 	ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos);  in girq_src_dis()
141 	TIMER_REGS->CTRL = 0U;  in timer_restart()
142 	TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN;  in timer_restart()
143 	TIMER_REGS->PRLD = countdown;  in timer_restart()
144 	TIMER_REGS->CTRL = TIMER_START_VAL;  in timer_restart()
154  * was on. We detect the timer is in the load state by checking the read-only
155  * count register and the START bit in the control register. If count register
156  * is 0 and the START bit is set then the timer has been started and is in the
161 	uint32_t ccr = TIMER_REGS->CNT;  in timer_count()
163 	if ((ccr == 0) && (TIMER_REGS->CTRL & MCHP_RTMR_CTRL_START)) {  in timer_count()
181  * RTMR counter register is read-only and is loaded from the preload
182  * register by a 0->1 transition of the control register start bit.
198 		 * global objects safe from pre-emption?  in sys_clock_set_timeout()
200 		TIMER_REGS->CTRL = 0U; /* stop timer */  in sys_clock_set_timeout()
208 		full_ticks = MAX_TICKS - 1;  in sys_clock_set_timeout()
210 		full_ticks = n - 1;  in sys_clock_set_timeout()
220 	TIMER_REGS->CTRL = 0u;  in sys_clock_set_timeout()
225 	temp += (cached_icr - ccr);  in sys_clock_set_timeout()
229 	partial_cycles = CYCLES_PER_TICK - (total_cycles % CYCLES_PER_TICK);  in sys_clock_set_timeout()
234 		temp -= TIMER_ADJUST_CYCLES;  in sys_clock_set_timeout()
245  * We must make sure bit[31] is 0 in the return value.
258 	elapsed = (int32_t)total_cycles - (int32_t)last_announcement;  in sys_clock_elapsed()
260 		elapsed = -1 * elapsed;  in sys_clock_elapsed()
263 	ticks += cached_icr - ccr;  in sys_clock_elapsed()
292 	/* handle wrap by using (power of 2) - 1 mask */  in xec_rtos_timer_isr()
293 	ticks = total_cycles - last_announcement;  in xec_rtos_timer_isr()
305 /* Non-tickless kernel build. */
336  * 1. Kernel call to k_cycle_get_32() -> arch_k_cycle_get_32() -> here.
351 	ret = (total_cycles + (cached_icr - ccr)) & TIMER_COUNT_MASK;  in sys_clock_cycle_get_32()
368 	TIMER_REGS->CTRL = 0U;  in sys_clock_disable()
380  * 32-bit basic timer 0 configured for 1MHz count up, auto-reload,
389 	uint32_t start = BTMR32_0_REGS->CNT;  in arch_busy_wait()
392 		uint32_t curr = BTMR32_0_REGS->CNT;  in arch_busy_wait()
394 		if ((curr - start) >= usec_to_wait) {  in arch_busy_wait()
408 	TIMER_REGS->CTRL = 0u;  in sys_clock_driver_init()
426 	PCR_XEC_REGS->SLP_EN[BTMR32_0_PCR_REG_IDX] &= ~BIT(BTMR32_0_PCR_BITPOS);  in sys_clock_driver_init()
428 	BTMR32_0_REGS->CTRL = MCHP_BTMR_CTRL_SOFT_RESET;  in sys_clock_driver_init()
429 	BTMR32_0_REGS->CTRL = btmr_ctrl;  in sys_clock_driver_init()
430 	BTMR32_0_REGS->PRLD = UINT32_MAX;  in sys_clock_driver_init()
435 	while (TIMER_REGS->CNT == 0) {  in sys_clock_driver_init()
439 	BTMR32_0_REGS->CTRL = btmr_ctrl;  in sys_clock_driver_init()