| /Zephyr-latest/dts/bindings/display/ |
| D | solomon,ssd16xx-common.yaml | 65 description: Gate driving voltage values
83 gate-line-width:
85 description: Gate line width override.
|
| D | sitronix,st7789v.yaml | 30 description: Gate Control
|
| D | sitronix,st7796s.yaml | 44 gate scan mode
|
| /Zephyr-latest/boards/shields/waveshare_epaper/ |
| D | waveshare_epaper_gdeh029a1.overlay | 36 gate-line-width = <0x08>;
49 gate-line-width = <0x08>;
|
| D | waveshare_epaper_gdeh0213b1.overlay | 36 gate-line-width = <0x08>;
51 gate-line-width = <0x08>;
|
| D | waveshare_epaper_gdeh0213b72.overlay | 36 gate-line-width = <0x0a>;
59 gate-line-width = <0x0a>;
|
| /Zephyr-latest/soc/nxp/imx/imx7d/ |
| D | soc.c | 39 /* Enable clock gate for IP bridge and IO mux */ in SOC_ClockInit()
46 /* Enable clock gate for RDC */ in SOC_ClockInit()
62 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
69 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
76 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
220 /* Enable clock gate for MU*/ in nxp_mcimx7_mu_config()
|
| D | soc_clk_freq.h | 51 /*! @brief CCM CCGR gate control. */
|
| /Zephyr-latest/samples/basic/custom_dts_binding/dts/bindings/ |
| D | power-switch.yaml | 13 The GPIO connected to the gate driver for the MOSFET.
|
| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 32 * The M7 core is running at domain 1, now enable the clock gate of the following IP/BUS/PLL in SOC_RdcInit()
46 /* Enable the CCGR gate for SysPLL1 in Domain 1 */ in SOC_RdcInit()
48 /* Enable the CCGR gate for SysPLL2 in Domain 1 */ in SOC_RdcInit()
50 /* Enable the CCGR gate for SysPLL3 in Domain 1 */ in SOC_RdcInit()
53 /* Enable the CCGR gate for VideoPLL1 in Domain 1 */ in SOC_RdcInit()
|
| /Zephyr-latest/dts/bindings/clock/ |
| D | raspberrypi,pico-clock.yaml | 14 description: Clock gate information
|
| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | soc.c | 28 /* gate off all aggregated outputs */ in soc_ecia_init()
30 /* gate on GIRQ's that are aggregated only */ in soc_ecia_init()
|
| /Zephyr-latest/boards/phytec/reel_board/ |
| D | reel_board.dts | 72 gate-line-width = <0x08>;
87 gate-line-width = <0x08>;
|
| D | reel_board_nrf52840_2.overlay | 53 gate-line-width = <0x0a>;
78 * number of Gate Pulses (length) : 3 3 0 0
97 gate-line-width = <0x0a>;
|
| /Zephyr-latest/dts/bindings/i2c/ |
| D | ite,common-i2c.yaml | 93 clock-gate-offset:
97 The clock gate offsets combine the register offset from
|
| /Zephyr-latest/drivers/fpga/ |
| D | Kconfig | 7 bool "Field-Programmable Gate Array (FPGA) drivers"
|
| /Zephyr-latest/include/zephyr/dt-bindings/i2c/ |
| D | it8xxx2-i2c.h | 12 * The clock gate offsets combine the register offset from ECPM_BASE and the
|
| /Zephyr-latest/samples/basic/custom_dts_binding/ |
| D | README.rst | 25 :zephyr_file:`samples/basic/custom_dts_binding/dts/bindings/power-switch.yaml`. The gate driver for
|
| /Zephyr-latest/boards/particle/boron/ |
| D | particle_boron.dts | 21 * single inverter gate -- requires a definition below,
|
| /Zephyr-latest/dts/bindings/base/ |
| D | base.yaml | 57 description: Clock gate information
|
| /Zephyr-latest/samples/net/sockets/txtime/src/ |
| D | main.c | 428 * GCL list 0 'set' gate open: Txq1 (default queue), in set_qbv_params()
431 * GCL list 1 'set' gate open: Txq0 (background queue) in set_qbv_params()
435 /* Turn on the gate control to first two gates (just for demo in set_qbv_params()
463 "gate control list", "", ret, i); in set_qbv_params()
478 "gate control list", " len", ret, i); in set_qbv_params()
|
| /Zephyr-latest/soc/nxp/imxrt/imxrt10xx/ |
| D | lpm_rt1064.c | 121 /* Wait for flexspi to be inactive, and gate the clock */ in flexspi_enter_critical()
127 /* Disable clock gate of flexspi2. */ in flexspi_enter_critical()
132 /* Wait for flexspi to be inactive, and gate the clock */ in flexspi_enter_critical()
146 /* Enable clock gate of flexspi2. */ in flexspi_exit_critical()
|
| /Zephyr-latest/dts/riscv/ite/ |
| D | it81xx2.dtsi | 366 clock-gate-offset = <CGC_OFFSET_SMBA>;
383 clock-gate-offset = <CGC_OFFSET_SMBB>;
400 clock-gate-offset = <CGC_OFFSET_SMBC>;
416 clock-gate-offset = <CGC_OFFSET_SMBD>;
431 clock-gate-offset = <CGC_OFFSET_SMBE>;
446 clock-gate-offset = <CGC_OFFSET_SMBF>;
|
| /Zephyr-latest/include/zephyr/arch/x86/ia32/ |
| D | arch.h | 93 * a task gate instead of an interrupt gate. fnc parameter will be
111 * The @a d argument specifies the privilege level for the interrupt-gate
|
| /Zephyr-latest/arch/x86/core/ia32/ |
| D | intstub.S | 81 * The gen_idt tool creates an interrupt-gate descriptor for
335 * Interrupt-gate descriptors are statically created for all slots in the IDT
352 * The gen_idt tool creates an interrupt-gate descriptor for all
|
