| /Zephyr-latest/dts/bindings/usb/ |
| D | renesas,smartbond-usbd.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "renesas,smartbond-usbd"
8 include: usb-ep.yaml
11 dma-min-transfer-size:
14 Minimum transfer size required to engage DMA.
16 ep-out-buf-size:
20 Buffer size for OUT end points 0-3.
22 fifo-read-threshold:
25 RX FIFO is 64 bytes. When endpoint size is greater then 64,
26 FIFO warning interrupt is enabled to allow read incoming data
[all …]
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| /Zephyr-latest/dts/bindings/serial/ |
| D | zephyr,nus-uart.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,nus-uart"
9 tx-fifo-size:
13 Size of the virtual UART TX FIFO
15 rx-fifo-size:
19 Size of the virtual UART RX FIFO
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| D | zephyr,uart-emul.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,uart-emul"
8 include: uart-controller.yaml
11 tx-fifo-size:
15 Size of the virtual UART TX FIFO
17 rx-fifo-size:
21 Size of the virtual UART RX FIFO
29 latch-buffer-size:
33 Size of the virtual UART latch buffer.
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| D | zephyr,cdc-acm-uart.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "zephyr,cdc-acm-uart"
8 include: uart-controller.yaml
10 on-bus: usb
13 tx-fifo-size:
17 Size of the virtual CDC ACM UART TX FIFO
19 rx-fifo-size:
23 Size of the virtual CDC ACM UART RX FIFO
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| D | infineon,xmc4xxx-uart.yaml | 3 compatible: "infineon,xmc4xxx-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
11 input-src:
20 - "DX0A"
21 - "DX0B"
22 - "DX0C"
23 - "DX0D"
24 - "DX0E"
25 - "DX0F"
26 - "DX0G"
[all …]
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| D | altr,jtag-uart.yaml | 3 compatible: "altr,jtag-uart"
5 include: uart-controller.yaml
11 write-fifo-depth:
15 Buffer size of transmit fifo. This used to implement irq_tx_complete.
16 Must be same as Write FIFO: Buffer depth (bytes) in platform designer.
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| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/common/ |
| D | edtt_driver_bsim.c | 4 * SPDX-License-Identifier: Apache-2.0
32 (EDTT_IF_RECHECK_DELTA * MSEC_PER_SEC - 1)
36 /* In this mode, when the EDTTool closes the FIFO we automatically terminate
43 static int fifo[2] = { -1, -1 }; variable
48 static int fifo_low_level_read(uint8_t *bufptr, int size);
81 * Attempt to read size bytes thru the EDTT IF into the buffer <*ptr>
84 * If set to EDTTT_BLOCK it will block the calling thread until <size>
89 * Returns the amount of read bytes, or -1 on error
91 int edtt_read(uint8_t *ptr, size_t size, int flags) in edtt_read() argument
94 return -1; in edtt_read()
[all …]
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| /Zephyr-latest/tests/drivers/uart/uart_emul/ |
| D | uart_emul.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
16 euart1: uart-dummy-bus {
17 compatible = "zephyr,uart-emul";
19 current-speed = <0>;
20 rx-fifo-size = <256>;
[all …]
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| /Zephyr-latest/tests/subsys/logging/log_backend_uart/ |
| D | multi.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 zephyr,log-uart = &log_uarts;
13 compatible = "zephyr,log-uart";
17 euart0: uart-emul0 {
18 compatible = "zephyr,uart-emul";
20 current-speed = <0>;
21 rx-fifo-size = <256>;
22 tx-fifo-size = <256>;
25 euart1: uart-emul1 {
26 compatible = "zephyr,uart-emul";
[all …]
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| /Zephyr-latest/dts/bindings/dma/ |
| D | gd,gd32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 GD32 DMA controller with FIFO
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
[all …]
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| D | st,stm32-dma-v1.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 This DMA controller includes FIFO control registers.
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
[all …]
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nxp,dspi.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 include: ["spi-controller.yaml", "pinctrl-device.yaml"]
20 pcs-sck-delay:
26 sck-pcs-delay:
32 transfer-delay:
38 pinctrl-0:
41 nxp,rx-tx-chn-share:
48 ctar register selection range form 0-1 for master mode, 0 for slave mode
50 sample-point:
56 continuous-sck:
[all …]
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| D | xlnx,xps-spi-2.00.a.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "xlnx,xps-spi-2.00.a"
8 include: spi-controller.yaml
11 # https://github.com/Xilinx/device-tree-xlnx
20 xlnx,num-ss-bits:
24 - 1
25 - 2
26 - 3
27 - 4
31 xlnx,num-transfer-bits:
[all …]
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| /Zephyr-latest/drivers/i3c/ |
| D | Kconfig.stm32 | 3 # SPDX-License-Identifier: Apache-2.0
6 module-str = i3c_stm32
26 int "Status FIFO and control FIFO heap"
30 Configures the heap size for dynamically allocating the regions for
31 storing status FIFO and control FIFO words which will be used by the DMA.
33 during a single transfer. 2KB guarantees enough heap size for sending 256
|
| /Zephyr-latest/include/zephyr/sd/ |
| D | sdio.h | 4 * SPDX-License-Identifier: Apache-2.0
33 * @retval -EIO: I/O error
45 * @retval -ETIMEDOUT: card I/O timed out
46 * @retval -EIO: I/O error
51 * @brief Set block size of SDIO function
53 * Set desired block size for SDIO function, used by block transfers
55 * @param func: function to set block size for
56 * @param bsize: block size
57 * @retval 0 block size was set
58 * @retval -EINVAL: unsupported/invalid block size
[all …]
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| /Zephyr-latest/subsys/bluetooth/controller/util/ |
| D | mfifo.h | 2 * Copyright (c) 2018-2024 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
8 * Memory FIFO permitting enqueue at tail (last) and dequeue from head (first).
14 * buffer yet to be committed, exists in a limbo state - until committed.
17 * Invariant: last-index refers to the buffer that is safe to write while in
18 * limbo-state. Outside limbo state, last-index refers one buffer ahead of what
21 * There are essentially two APIs, distinguished by the buffer-type:
22 * API 1 Value-type : MFIFO_DEFINE(name1, sizeof(struct foo), cnt1);
23 * API 2 Pointer-type : MFIFO_DEFINE(name2, sizeof(void *), cnt2);
27 * ------+------------------------+----------------------
[all …]
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| /Zephyr-latest/drivers/i2c/ |
| D | Kconfig.it8xxx2 | 2 # SPDX-License-Identifier: Apache-2.0
17 bool "IT8XXX2 I2C FIFO mode"
20 This is an option to enable FIFO mode which can reduce
23 The I2C controller supports two 32-bytes FIFOs,
25 I2C FIFO mode of it8xxx2 can support I2C APIs including:
53 int "It is allowed to configure the size up to 2K bytes."
57 This is the command queue mode payload size which size
65 int "It is allowed to configure the size up to 2044 bytes."
|
| /Zephyr-latest/tests/subsys/shell/shell_backend_uart/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 euart0: uart-emul0 {
9 compatible = "zephyr,uart-emul";
11 current-speed = <0>;
12 rx-fifo-size = <256>;
13 tx-fifo-size = <256>;
|
| /Zephyr-latest/samples/subsys/logging/logger/ |
| D | bt.overlay | 4 * SPDX-License-Identifier: Apache-2.0
13 compatible = "zephyr,nus-uart";
14 rx-fifo-size = <1024>;
15 tx-fifo-size = <1024>;
|
| /Zephyr-latest/snippets/nus-console/ |
| D | nus-console.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
|
| /Zephyr-latest/samples/subsys/shell/shell_module/ |
| D | bt.overlay | 4 * SPDX-License-Identifier: Apache-2.0
10 zephyr,shell-uart = &bt_nus_console_uart;
14 compatible = "zephyr,nus-uart";
15 rx-fifo-size = <1024>;
16 tx-fifo-size = <1024>;
|
| /Zephyr-latest/doc/kernel/services/data_passing/ |
| D | fifos.rst | 6 A :dfn:`FIFO` is a kernel object that implements a traditional
7 first in, first out (FIFO) queue, allowing threads and ISRs
8 to add and remove data items of any size.
17 Any number of FIFOs can be defined (limited only by available RAM). Each FIFO is
20 A FIFO has the following key properties:
25 A FIFO must be initialized before it can be used. This sets its queue to empty.
27 FIFO data items must be aligned on a word boundary, as the kernel reserves
36 FIFO data items are restricted to single active instance across all FIFO
37 data queues. Any attempt to re-add a FIFO data item to a queue before
41 A data item may be **added** to a FIFO by a thread or an ISR.
[all …]
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| /Zephyr-latest/subsys/tracing/test/ |
| D | tracing_test.h | 4 * SPDX-License-Identifier: Apache-2.0
206 /* FIFO */
208 #define sys_port_trace_k_fifo_init_enter(fifo) sys_trace_k_fifo_init_enter(fifo) argument
210 #define sys_port_trace_k_fifo_init_exit(fifo) sys_trace_k_fifo_init_exit(fifo) argument
212 #define sys_port_trace_k_fifo_cancel_wait_enter(fifo) sys_trace_k_fifo_cancel_wait_enter(fifo) argument
214 #define sys_port_trace_k_fifo_cancel_wait_exit(fifo) sys_trace_k_fifo_cancel_wait_exit(fifo) argument
216 #define sys_port_trace_k_fifo_put_enter(fifo, data) sys_trace_k_fifo_put_enter(fifo, data) argument
218 #define sys_port_trace_k_fifo_put_exit(fifo, data) sys_trace_k_fifo_put_exit(fifo, data) argument
220 #define sys_port_trace_k_fifo_alloc_put_enter(fifo, data) \ argument
221 sys_trace_k_fifo_alloc_put_enter(fifo, data)
[all …]
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| /Zephyr-latest/drivers/ethernet/ |
| D | Kconfig.nxp_s32_gmac | 1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
22 must be a multiple of TX FIFO block size.
25 int "TX ring data buffer size"
29 Size, in bytes, of the TX data buffer. The size must be big enough to
39 must be a multiple of RX FIFO block size.
42 int "RX ring data buffer size"
46 Size, in bytes, of the RX data buffer. The size must be big enough to
54 This option specifies the zero-based index of the clock configuration
64 int "RX thread stack size"
[all …]
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| /Zephyr-latest/tests/drivers/uart/uart_async_api/boards/ |
| D | xmc45_relax_kit.overlay | 1 /* SPDX-License-Identifier: Apache-2.0 */
3 #include <zephyr/dt-bindings/dma/infineon-xmc4xxx-dma.h>
6 compatible = "infineon,xmc4xxx-uart";
7 current-speed = <921600>;
8 pinctrl-0 = <&uart_tx_p5_0_u2c0 &uart_rx_p5_1_u2c0>;
9 pinctrl-names = "default";
10 input-src = "DX0G";
12 interrupt-names = "tx", "rx";
14 dma-names = "tx", "rx";
15 fifo-start-offset = <0>;
[all …]
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