| /Zephyr-latest/dts/bindings/sensor/ |
| D | nxp,lpcmp.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP low-power analog comparator (LPCMP)
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 enable-output-pin:
20 Decide whether to enable the comparator is available in selected pin.
22 use-unfiltered-output:
25 Decide whether to use the unfiltered output.
27 enable-output-invert:
30 Decide whether to invert the comparator output.
32 hysteresis-level:
[all …]
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,s32k3-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
49 pinctrl-0 = <&uart0_default>;
[all …]
|
| D | nxp,rt-iocon-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
17 slew-rate = "normal";
18 drive-strength = "normal";
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
38 input-enable: IOCON_IBENA=1
40 compatible: "nxp,rt-iocon-pinctrl"
[all …]
|
| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
[all …]
|
| D | microchip,mec5-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
22 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
25 - bias-disable: Disable pull-up/down (default behavior, not required).
26 - bias-pull-down: Enable pull-down resistor.
27 - bias-pull-up: Enable pull-up resistor.
28 - drive-push-pull: Output driver is push-pull (default, not required).
29 - drive-open-drain: Output driver is open-drain.
30 - output-high: Set output state high when pin configured.
31 - output-low: Set output state low when pin configured.
[all …]
|
| D | nxp,lpc-iocon-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
[all …]
|
| D | nordic,nrf-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 node to route UART0 RX to pin P0.1 and enable the pull-up resistor on the
20 /* You can put this in places like a board-pinctrl.dtsi file in
35 /* both P0.3 and P0.4 are configured with pull-up */
36 bias-pull-up;
43 state. You would specify the low-power configuration for the same device
52 include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h header file.
55 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
58 - bias-disable: Disable pull-up/down (default behavior, not required).
59 - bias-pull-up: Enable pull-up resistor.
[all …]
|
| /Zephyr-latest/include/zephyr/drivers/sensor/ |
| D | mcux_lpcmp.h | 5 * SPDX-License-Identifier: Apache-2.0
10 * @brief Data structure for the NXP MCUX low-power analog comparator (LPCMP)
26 /** LPCMP output. */
34 /** LPCMP output rising event trigger. */
36 /** LPCMP output falling event trigger. */
50 * LPCMP internal DAC enable.
52 * 1b: enable
58 * 1b: enable
63 /** LPCMP internal DAC output voltage value. */
66 /** LPCMP internal filter sample enable. */
[all …]
|
| /Zephyr-latest/dts/bindings/input/ |
| D | cirque,pinnacle-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 data-ready-gpios:
8 type: phandle-array
20 - "1x"
21 - "2x"
22 - "3x"
23 - "4x"
25 data-mode:
29 Data output mode in which position is reported. In the relative mode
33 - "absolute"
[all …]
|
| /Zephyr-latest/dts/bindings/comparator/ |
| D | nxp,kinetis-acmp.yaml | 3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
[all …]
|
| /Zephyr-latest/tests/drivers/build_all/input/ |
| D | app.overlay | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
17 #io-channel-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
26 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
32 gpio-controller;
34 #gpio-cells = <0x2>;
[all …]
|
| /Zephyr-latest/drivers/pinctrl/ |
| D | pinctrl_mchp_mec5.c | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
21 /* DT enable booleans take precedence over disable booleans.
22 * We initially clear alternate output disable allowing us to set output state
23 * in the control register. Hardware sets output state bit in both control and
24 * parallel output register bits. Alternate output disable only controls which
27 * alternate function is input or bi-directional.
28 * Note 1: hardware allows input and output to be simultaneously enabled.
41 return -EINVAL; in mec5_config_pin()
[all …]
|
| D | pinctrl_mchp_xec.c | 2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
7 * SPDX-License-Identifier: Apache-2.0
16 * Microchip XEC: each GPIO pin has two 32-bit control register.
17 * The first 32-bit register contains all pin features except
41 val |= ((drvstr - 1u) << MCHP_GPIO_CTRL2_DRV_STR_POS); in config_drive_slew()
48 regs->CTRL2[idx] = (regs->CTRL2[idx] & ~msk) | (val & msk); in config_drive_slew()
53 * None, weak pull-up, weak pull-down, or repeater mode (both pulls enabled).
55 * If the no-bias boolean is set then disable internal pulls.
56 * If pull up and/or down is set enable the respective pull or both for what
81 * DT enable booleans take precedence over disable booleans.
[all …]
|
| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | nrf-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole nRF pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 19-23: Reserved.
15 * - 18: Associated peripheral belongs to GD FAST ACTIVE1 (nRF54H only)
16 * - 17: Clockpin enable.
17 * - 16: Pin inversion mode.
18 * - 15: Pin low power mode.
19 * - 14..11: Pin output drive configuration.
20 * - 10..9: Pin pull configuration.
[all …]
|
| /Zephyr-latest/drivers/input/ |
| D | input_ite_it8801_kbd.c | 4 * SPDX-License-Identifier: Apache-2.0
43 /* Keyboard scan in interrupt enable register */
56 const struct kbd_it8801_config *config = dev->config; in kbd_it8801_drive_column()
61 /* Tri-state all outputs. KSO[22:11, 6:0] output high */ in kbd_it8801_drive_column()
64 /* Assert all outputs. KSO[22:11, 6:0] output low */ in kbd_it8801_drive_column()
67 /* Selected KSO[22:11, 6:0] output low, all others KSO output high */ in kbd_it8801_drive_column()
68 kso_val = config->kso_mapping[col]; in kbd_it8801_drive_column()
71 ret = i2c_reg_write_byte_dt(&config->i2c_dev, config->reg_ksomcr, kso_val); in kbd_it8801_drive_column()
80 const struct kbd_it8801_config *const config = dev->config; in kbd_it8801_read_row()
84 ret = i2c_reg_read_byte_dt(&config->i2c_dev, config->reg_ksidr, &value); in kbd_it8801_read_row()
[all …]
|
| /Zephyr-latest/drivers/pwm/ |
| D | pwm_mchp_xec_bbled.c | 4 * SPDX-License-Identifier: Apache-2.0
51 * Puse_OFF_width = (1/Fpwm) * (256 - duty_cycle) seconds
52 * where duty_cycle is an 8-bit value 0 to 255.
53 * Prescale is derived from DELAY register LOW_DELAY 12-bit field
54 * Duty cycle is derived from LIMITS register MINIMUM 8-bit field
61 * BBLED PWM mode duty cycle specified by 8-bit MIN field of the LIMITS register
97 /* Output delay in clocks for initial enable and enable on resume from sleep
140 * DELAY.LO = pre-scaler = [0, 4095]
147 const struct pwm_bbled_xec_config * const cfg = dev->config; in xec_pwmbb_progam_pwm()
148 struct bbled_regs * const regs = cfg->regs; in xec_pwmbb_progam_pwm()
[all …]
|
| /Zephyr-latest/drivers/display/ |
| D | display_st7796s.c | 4 * SPDX-License-Identifier: Apache-2.0
45 uint8_t doca[8]; /* Display output ctrl */
49 uint8_t te_mode; /* Tearing enable mode */
50 uint32_t te_delay; /* Tearing enable delay */
57 const struct st7796s_config *config = dev->config; in st7796s_send_cmd()
59 return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, in st7796s_send_cmd()
72 addr_data[1] = sys_cpu_to_be16(x + width - 1); in st7796s_set_cursor()
82 addr_data[1] = sys_cpu_to_be16(y + height - 1); in st7796s_set_cursor()
100 const struct st7796s_config *config = dev->config; in st7796s_get_pixelfmt()
103 * Invert the pixel format for 8-bit 8080 Parallel Interface. in st7796s_get_pixelfmt()
[all …]
|
| /Zephyr-latest/include/zephyr/drivers/ |
| D | gpio.h | 2 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * Copyright (c) 2015-2016 Intel Corporation.
7 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/gpio/gpio.h>
43 * @name GPIO input/output configuration flags
50 /** Enables pin as output, no change to the output state. */
53 /** Disables pin for both input and output. */
58 /* Initializes output to a low state. */
61 /* Initializes output to a high state. */
64 /* Initializes output based on logic level */
[all …]
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_sifive.c | 2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
44 unsigned int invert; member
51 /* multi-level encoded interrupt corresponding to pin 0 */
65 ((const struct gpio_sifive_config * const)(dev)->config)
67 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
69 ((struct gpio_sifive_data *)(dev)->data)
98 return (plic_irq - base_irq); in gpio_sifive_plic_to_pin()
108 uint8_t pin = 1 + (riscv_plic_get_irq() - in gpio_sifive_irq_handler()
[all …]
|
| D | gpio_intel.c | 2 * Copyright (c) 2018-2019 Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
17 * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18 * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 ((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
[all …]
|
| /Zephyr-latest/drivers/dai/nxp/esai/ |
| D | esai.h | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/dai/esai.h>
32 /* used to fetch the depth of the FIFO. If the "fifo-depth" property is
40 /* used to fetch the TX FIFO watermark value. If the "tx-fifo-watermark"
46 /* used to fetch the RX FIFO watermark value. If the "rx-fifo-watermark"
61 /* used to fetch the word width. If the "word-width" property is not specified,
71 /* invert a clock's polarity. This works because a clock's polarity
76 #define _ESAI_SLOT_WORD_WIDTH_IS_VALID(width) (!(((width) - 8) % 4))
88 ((w) < 24 ? ((s) - (w) + (((w) - 8) / 4)) : ((s) < 32 ? 0x1e : 0x1f))
94 #define ESAI_WORD_ALIGNMENT(word_width) ((32 - (word_width)) / 4)
[all …]
|
| /Zephyr-latest/doc/releases/ |
| D | migration-guide-4.0.rst | 39 to define default flash and ram partitioning based on TF-M.
60 specify it using the west ``--runner`` or ``-r`` option. (:github:`75284`)
61 * ADC: Domain clock needs to be explicitly defined if property st,adc-clock-source = <ASYNC> is use…
85 Trusted Firmware-M
130 Chip variants with open-drain outputs (``mcp23x09``, ``mcp23x18``) now correctly reflect this in
134 * The ``power-domain`` property has been removed in favor of ``power-domains``.
136 ``power-domain-names`` is also available to optionally name each entry in
137 ``power-domains``. The number of cells in the ``power-domains`` property need
138 to be defined using ``#power-domain-cells``.
143 * For all STM32 ADC that selects an asynchronous clock through ``st,adc-clock-source`` property,
[all …]
|
| D | release-notes-3.7.rst | 10 This release is the last non-maintenance 3.x release and, as such, will be the next
18 * A long-awaited :ref:`HTTP Server <http_server_interface>` library, and associated service API,
21 * :ref:`POSIX support <posix_support>` has been extended, with most Options of the IEEE 1003-2017
25 * Bluetooth Host has been extended with support for the Nordic UART Service (NUS), Hands-free Audio
29 :ref:`read-then-decode approach <sensor-read-and-decode>` that enables more types of sensors and
35 * Trusted Firmware-M (TF-M) 2.1.0 and Mbed TLS 3.6.0 have been integrated into Zephyr.
39 1588) allows to synchronize time across devices with sub-microsecond accuracy.
52 * 1-Wire
71 :ref:`pinctrl-guide` for more details.
88 * CVE-2024-3077 `Zephyr project bug tracker GHSA-gmfv-4vfh-2mh8
[all …]
|
| /Zephyr-latest/drivers/regulator/ |
| D | regulator_npm1300.c | 3 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/regulator/npm1300.h>
96 /* Linear range for output voltage, common for all bucks and LDOs on this device */
101 const struct regulator_npm1300_config *config = dev->config; in regulator_npm1300_count_voltages()
103 switch (config->source) { in regulator_npm1300_count_voltages()
116 const struct regulator_npm1300_config *config = dev->config; in regulator_npm1300_list_voltage()
118 switch (config->source) { in regulator_npm1300_list_voltage()
125 return -EINVAL; in regulator_npm1300_list_voltage()
131 const struct regulator_npm1300_config *config = dev->config; in retention_set_voltage()
136 switch (config->source) { in retention_set_voltage()
[all …]
|
| /Zephyr-latest/drivers/video/ |
| D | ov2640.c | 4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/video-controls.h>
126 #define COM7_ZOOM_EN 0x04 /* Enable Zoom */
127 #define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
131 #define COM8_BNDF_EN 0x20 /* Enable Banding filter */
143 #define CTRL1_AWB 0x08 /* Enable AWB */
170 { COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
174 { COM10, 0x00 }, /* Invert VSYNC */
370 * The sensor output image can be scaled with OUTW/OUTH
407 { 0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
[all …]
|
