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/Zephyr-latest/dts/bindings/clock/
Dst,stm32-lse-clock.yaml11 driving-capability:
15 LSE driving capability, within the range 0 to 3.
16 0 represents the lowests driving capability, 3
/Zephyr-latest/dts/bindings/pwm/
Dnxp,ftm-pwm.yaml26 * system: it's the bus interface clock driving the FTM module. Usually
33 driving the FTM module. Refer to the chip specific documentation for
/Zephyr-latest/dts/bindings/display/
Dsolomon,ssd16xx-common.yaml65 description: Gate driving voltage values
69 description: Source driving voltage values
Dlcd-controller.yaml4 # Common fields for LCD controllers driving a panel.
Distech,ist3931.yaml42 description: LCD bias ratio of the voltage required for driving the LCD
/Zephyr-latest/drivers/spi/
DKconfig.rpi_pico12 Enable driving SPI via PIO on the PICO
/Zephyr-latest/dts/bindings/watchdog/
Dnxp,fs26-wdog.yaml15 The FS26 uses a 32-bit SPI interface. The MCU is the primary driving MOSI and
16 FS26 is the secondary driving MISO. Therefore the FS26 devicetree node must be
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Drenesas-rz-gpio.h13 * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
15 * - Bit 9..8: Pin driving ability value
/Zephyr-latest/samples/basic/servo_motor/dts/bindings/
Dpwm-servo.yaml14 description: PWM specifier driving the servo motor.
/Zephyr-latest/drivers/gpio/
DKconfig.mmio3212 driving an LED, or chip-select line for an SPI device.
/Zephyr-latest/dts/bindings/sensor/
Dst,vl53l1x.yaml14 Driving the XSHUT pin low puts the VL53L1X into hardware
/Zephyr-latest/samples/boards/nordic/nrf_led_matrix/
DREADME.rst18 of GPIOs available for driving an LED matrix. To do it, one needs to add an
/Zephyr-latest/dts/bindings/spi/
Dmicrochip,xec-qmspi.yaml58 description: Delay in system clocks from CS# de-assertion to driving HOLD# and WP#
Dmicrochip,xec-qmspi-ldma.yaml71 Delay in QMSPI main clocks from CS# de-assertion to driving HOLD#
/Zephyr-latest/dts/bindings/haptics/
Dti,drv2605.yaml32 Selects the feedback gain ratio between braking gain and driving gain.
/Zephyr-latest/soc/ene/kb1200/reg/
Dgpio.h28 volatile uint32_t GPIODC; /*Driving Control Register */
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c24 /* port driving select control */
132 /* Driving current selection. */ in pinctrl_it8xxx2_set()
136 /* Driving current selects low. */ in pinctrl_it8xxx2_set()
139 /* Driving current selects high. */ in pinctrl_it8xxx2_set()
/Zephyr-latest/soc/ite/ec/common/
Dpinctrl_soc.h76 /* Pin driving select control */
117 * @brief Utility macro to obtain configuration of driving current selection.
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_mco.c26 /* clock subsystem driving this peripheral */
/Zephyr-latest/dts/bindings/pinctrl/
Dnuvoton,numaker-pinctrl.yaml73 Set the driving strength of a pin. Hardware default configuration is low and
Dpincfg-node.yaml105 enable output on a pin without actively driving it (e.g. enable an output
/Zephyr-latest/drivers/serial/
Duart_stm32.h32 /* clock subsystem driving this peripheral */
/Zephyr-latest/drivers/display/
Dssd1306_regs.h87 * Timing and Driving Scheme Setting Command Table
/Zephyr-latest/soc/atmel/sam/common/
DKconfig24 The main clock is being used to drive the PLL, and thus driving the
/Zephyr-latest/dts/bindings/gpio/
Dnordic,nrf-gpio-forwarder.yaml13 core is responsible for configuring the pins and driving them as needed.

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