1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  FS26 System Basis Chip (SBC) watchdog driver.
6
7  The FS26 features multiple voltage regulators to supply the microcontroller,
8  peripheral ICs and communication interfaces. The FS26 also offers various
9  functionalities for system control and monitoring, including a configurable
10  watchdog counter to ensure the microcontroller is able to communicate with the
11  FS26, which can react to any failure condition and place the system in a safe
12  state. This driver covers only the watchdog functionality of FS26. The rest
13  of the functionalities are not implemented.
14
15  The FS26 uses a 32-bit SPI interface. The MCU is the primary driving MOSI and
16  FS26 is the secondary driving MISO. Therefore the FS26 devicetree node must be
17  in a SPI bus. For example, if FS26 is connected to spi3 bus, on Chip Select 0:
18
19    &spi3 {
20      // here there should be spi3 properties as needed
21      status = "okay";
22
23      fs26_wdt: watchdog@0 {
24        compatible = "nxp,fs26-wdog";
25        reg = <0>;
26        spi-max-frequency = <DT_FREQ_M(5)>;
27        type = "challenger";
28        int-gpios = <&gpioa_h 3 GPIO_ACTIVE_LOW>;
29        status = "okay";
30      };
31    };
32
33  When an FS26 internal interrupt occurs, the INTB pin generates a pulse to
34  inform the microcontroller. The driver masks all interrupt sources except for
35  bad watchdog refresh (BAD_WD_M). The GPIO pin where the interrupt signal is
36  received must be configured from devicetree. In the example above, this is
37  indicated through int-gpios property. It is also required to configure the
38  external interrupt controller to receive interrupts on this pin.
39
40compatible: "nxp,fs26-wdog"
41
42include: spi-device.yaml
43
44properties:
45  type:
46    required: true
47    type: string
48    enum:
49      - simple
50      - challenger
51    description: |
52      Watchdog type enabled on this device.
53
54      The Challenger watchdog monitoring feature is enabled for ASIL D devices.
55      This mode is based on a question/answer process with the microcontroller.
56
57      The Simple watchdog monitoring feature is enabled for ASIL B devices. This
58      mode uses a unique seed.
59
60  int-gpios:
61    type: phandle-array
62    required: true
63    description: |
64      GPIO to use to receive external interrupts from INTB signal.
65