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/Zephyr-Core-3.5.0/dts/bindings/dma/
Ddmamux-controller.yaml4 # Common fields for DMAMUX controllers
8 bus: dmamux
19 description: Number of DMAMUX output request channels supported by the controller
23 description: Number of DMAMUX Request generator supported by the controller
29 Number of DMAMUX Peripheral Request Line inputs supported by the controller
Dnxp,mcux-edma.yaml14 Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
26 dmamux-reg-offset:
30 The offset value for obtaining DMAMUX register index from DMAMUX channel.
31 Default value means DMAMUX channel is identical with DMAMUX register index
57 description: Number of items to expect in a DMAMUX specifier
Dst,stm32-dmamux.yaml5 STM32 DMAMUX controller
7 The STM32 DMAMUX is a direct memory access multiplexer
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
45 dmamux1: dmamux@40020800 {
46 compatible = "st,stm32-dmamux";
61 compatible: "st,stm32-dmamux"
63 include: dmamux-controller.yaml
77 …pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dmamux.yaml
Dst,stm32-dma.yaml11 or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
32 offset in the table of channels when mapping to a DMAMUX
Dst,stm32-bdma.yaml61 dma-names = "dmamux";
82 offset in the table of channels when mapping to a DMAMUX
/Zephyr-Core-3.5.0/dts/bindings/qspi/
Dst,stm32-qspi.yaml41 hold a phandle reference to the dma controller (not the DMAMUX even if present),
45 When a DMAMUX is present and enabled, the channel is the dma one
46 (not dmamux channel). The request is given by the DMAMUX (no 'features' required).
51 For example with a DMAMUX for TX/RX on QSPI like stm32wb55 (no 'features')
/Zephyr-Core-3.5.0/drivers/dma/
DKconfig.stm3252 Enable DMAMUX support.
71 int "STM32 DMAMUX init priority"
75 DMAMUX driver device must be init'd after the DMA (CONFIG_DMA_INIT_PRIORITY)
76 DMAMUX driver device initialization priority is greater than DMA one's
Ddmamux_stm32.c9 * @brief Common part of DMAMUX drivers for stm32.
32 /* this is the configuration of one dmamux channel */
40 /* the table of all the dmamux channel */
47 /* this is the configuration of the dmamux IP */
147 /* device is the dmamux, id is the dmamux channel from 0 */ in dmamux_stm32_configure()
176 * This dmamux channel 'id' is now used for this peripheral request in dmamux_stm32_configure()
181 LOG_ERR("cannot configure the dmamux."); in dmamux_stm32_configure()
185 /* set the Request Line ID to this dmamux channel i */ in dmamux_stm32_configure()
186 DMAMUX_Channel_TypeDef *dmamux = in dmamux_stm32_configure() local
190 LL_DMAMUX_SetRequestID(dmamux, id, request_id); in dmamux_stm32_configure()
[all …]
Ddma_stm32.h21 int mux_channel; /* stores the dmamux channel */
43 uint8_t offset; /* position in the list of dmamux channel list */
/Zephyr-Core-3.5.0/tests/drivers/dma/loop_transfer/boards/
Dstm32mp157c_dk2.overlay15 &dmamux {
19 test_dma0: &dmamux {
/Zephyr-Core-3.5.0/dts/bindings/ospi/
Dst,stm32-ospi.yaml52 - 41: slot number (request which could be given by the DMAMUX)
56 - On series supporting DMAMUX, the DMA phandle should be provided
57 but DMAMUX node should also be enabled in the DTS.
/Zephyr-Core-3.5.0/tests/drivers/dma/chan_blen_transfer/boards/
Dstm32mp157c_dk2.overlay13 test_dma0: &dmamux {
/Zephyr-Core-3.5.0/tests/drivers/adc/adc_dma/boards/
Dnucleo_u575zi_q.overlay10 dma-names = "dmamux";
Dnucleo_h743zi.overlay12 dma-names = "dmamux";
/Zephyr-Core-3.5.0/dts/arm/st/g4/
Dstm32g431.dtsi24 dmamux1: dmamux@40020800 {
/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h743.dtsi24 dmamux1: dmamux@40020800 {
28 dmamux2: dmamux@58025800 {
Dstm32h750.dtsi24 dmamux1: dmamux@40020800 {
28 dmamux2: dmamux@58025800 {
Dstm32h745.dtsi31 dmamux1: dmamux@40020800 {
35 dmamux2: dmamux@58025800 {
Dstm32h7a3.dtsi27 dmamux1: dmamux@40020800 {
31 dmamux2: dmamux@58025800 {
Dstm32h723.dtsi58 dmamux1: dmamux@40020800 {
62 dmamux2: dmamux@58025800 {
/Zephyr-Core-3.5.0/dts/arm/st/g0/
Dstm32g050.dtsi40 dmamux1: dmamux@40020800 {
Dstm32g070.dtsi49 dmamux1: dmamux@40020800 {
Dstm32g071.dtsi33 dmamux1: dmamux@40020800 {
Dstm32g051.dtsi79 dmamux1: dmamux@40020800 {
/Zephyr-Core-3.5.0/dts/arm/st/c0/
Dstm32c0.dtsi316 /* DMAMUX clock is enabled as long as DMA1 is enabled */
317 dmamux1: dmamux@40020800 {
318 compatible = "st,stm32-dmamux";

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