1# Copyright (c) 2023 Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 BDMA controller
6
7  The STM32 BDMA is a general-purpose direct memory access controller
8  capable of supporting 5 or 6 or 7 or 8 independent BDMA channels.
9  Each channel can have up to 8 requests.
10  BDMA clients connected to the STM32 BDMA controller must use the format
11  described in the dma.txt file, using a four-cell specifier for each
12  channel: a phandle to the BDMA controller plus the following four integer cells:
13    1. channel: the bdma stream from 0 to <bdma-requests>
14    2. slot: bdma request
15    3. channel-config: A 32bit mask specifying the BDMA channel configuration
16    which is device dependent:
17        -bit 6-7 : Direction  (see dma.h)
18               0x0: MEM to MEM
19               0x1: MEM to PERIPH
20               0x2: PERIPH to MEM
21               0x3: reserved for PERIPH to PERIPH
22        -bit 9 : Peripheral Increment Address
23               0x0: no address increment between transfers
24               0x1: increment address between transfers
25        -bit 10 : Memory Increment Address
26               0x0: no address increment between transfers
27               0x1: increment address between transfers
28        -bit 11-12 : Peripheral data size
29               0x0: Byte (8 bits)
30               0x1: Half-word (16 bits)
31               0x2: Word (32 bits)
32               0x3: reserved
33        -bit 13-14 : Memory data size
34               0x0: Byte (8 bits)
35               0x1: Half-word (16 bits)
36               0x2: Word (32 bits)
37               0x3: reserved
38        -bit 15: Peripheral Increment Offset Size
39               0x0: offset size is linked to the peripheral bus width
40               0x1: offset size is fixed to 4 (32-bit alignment)
41        -bit 16-17 : Priority level
42               0x0: low
43               0x1: medium
44               0x2: high
45               0x3: very high
46
47    examples for stm32h7
48     bdma1: dma-controller@58025400 {
49         compatible = "st,stm32-bdma";
50         ...
51         st,mem2mem;
52         dma-requests = <7>;
53         status = "disabled";
54        };
55
56  For the client part, example for STM32H743 on BDMA1 instance
57  using dmamux2
58
59    &adc3 {
60       dmas = < &dmamux2 0 17 0x2C80 >;
61       dma-names = "dmamux";
62    };
63
64compatible: "st,stm32-bdma"
65
66include: dma-controller.yaml
67
68properties:
69  reg:
70    required: true
71
72  interrupts:
73    required: true
74
75  st,mem2mem:
76    type: boolean
77    description: If the BDMA controller supports memory to memory transfer
78
79  dma-offset:
80    type: int
81    description: >
82      offset in the table of channels when mapping to a DMAMUX
83      for 1st dma instance, offset is 0,
84      for 2nd dma instance, offset is the nb of dma channels of the 1st dma,
85      for 3rd dma instance, offset is the nb of dma channels of the 2nd dma
86      plus the nb of dma channels of the 1st dma instance, etc.
87
88  "#dma-cells":
89    const: 4
90
91# Parameter syntax of stm32 follows the dma client dts syntax
92# in the Linux kernel declared in
93# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
94
95dma-cells:
96  - channel
97  - slot
98  - channel-config
99