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/Zephyr-Core-3.5.0/dts/bindings/dma/
Dst,stm32-dma-v2bis.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2bis) for the stm32F0, stm32F1 and stm32L1 soc families
7 This DMA controller includes several channels with different requests.
8 All the requests ar ORed before entering the DMA, so that only one request
10 DMA clients connected to the STM32 DMA controller must use the format
11 described in the dma.txt file, using a 2-cell specifier for each
12 channel: a phandle to the DMA controller plus the following four integer cells:
13 1. channel: the dma stream from 1 to <dma-requests>
14 2. channel-config: A 32bit mask specifying the DMA channel configuration
15 A name custom DMA flags for channel configuration is used
[all …]
Dst,stm32-dma-v2.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V2)
8 This DMA controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a 3-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
15 1. channel: the dma stream from 1 to <dma-requests>
[all …]
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
9 Each channel can have up to 8 requests.
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
[all …]
Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller (V1)
8 This DMA controller includes FIFO control registers.
9 DMA clients connected to the STM32 DMA controller must use the format
10 described in the dma.txt file, using a four-cell specifier for each
11 channel: a phandle to the DMA controller plus the following four integer cells:
12 1. channel: the dma stream from 0 to <dma-requests>
13 2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
[all …]
Dst,stm32u5-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller for the stm32U5 soc family
7 It is present on stm32U5 devices as a GP DMA
8 This controller includes several channels with different requests.
9 DMA clients connected to the STM32 DMA controller must use a three-cell
17 dma-names = "tx", "rx";
19 It is a phandle to the DMA controller plus the following three integer cells
20 1. channel: the stream or channel from 0 to (<dma-channels> - 1).
21 2. slot: DMA periph request ID, which is written in the REQSEL bits of the CxTR2
22 the slot is a value between <0> .. (<dma-requests> - 1).
[all …]
Ddmamux-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier (see dma V2)
16 dma-channels:
21 dma-generators:
25 dma-requests:
Ddma-controller.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for DMA controllers
8 bus: dma
11 "#dma-cells":
14 description: Number of items to expect in a DMA specifier
16 dma-channel-mask:
19 Bitmask of available DMA channels in ascending order that are
23 dma-channels:
25 description: Number of DMA channels supported by the controller
27 dma-requests:
[all …]
Dst,stm32-dma.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
8 capable of supporting 5 or 6 or 7 or 8 independent DMA channels.
9 Each stm32 soc with a DMA is of a special version type, which could be
12 or V2bis like stm32F1 or stm32L1, where requests are multiplexed
14 compatible: "st,stm32-dma"
16 include: dma-controller.yaml
27 description: If the DMA controller V1 supports memory to memory transfer
29 dma-offset:
[all …]
Dnxp,mcux-edma.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mcux-edma"
8 include: dma-controller.yaml
14 Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
15 that routes DMA sources
20 dma-channels:
23 dma-requests:
26 dmamux-reg-offset:
33 channel-gap:
41 description: If the DMA controller supports memory to memory transfer
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Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
8 capable of supporting independent DMA channels.
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
10 for each dmamux channel: a phandle to the DMA multiplexer plus the following 2 integer cells:
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/g4/
Dstm32g431.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g431", "st,stm32g4", "simple-bus";
13 dma1: dma@40020000 {
15 dma-requests = <6>;
18 dma2: dma@40020400 {
20 dma-requests = <6>;
21 dma-offset = <6>;
25 dma-channels = <12>;
Dstm32g491.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g491", "st,stm32g4", "simple-bus";
14 compatible = "st,stm32-fdcan";
16 reg-names = "m_can", "message_ram";
18 interrupt-names = "LINE_0", "LINE_1";
20 bosch,mram-cfg = <0x350 28 8 3 3 0 3 3>;
21 sample-point = <875>;
22 sample-point-data = <875>;
27 compatible = "st,stm32-timers";
32 interrupt-names = "brk", "up", "trgcom", "cc";
[all …]
/Zephyr-Core-3.5.0/doc/services/rtio/
Dindex.rst20 DMA transfer lists.
25 An application wishing to do complex DMA or interrupt driven operations today
27 no understanding in the DMA API of other Zephyr devices and how they relate.
30 hardware knowledge or leaky abstractions over DMA controllers. Neither is ideal.
32 To enable asynchronous operations, especially with DMA, a description of what
34 DMA features such as channels with priority, and sequences of transfers requires
37 Using DMA and/or interrupt driven I/O shouldn't dictate whether or not the
45 lock-free ring buffers acting as queues shared between the kernel and a userland
47 create concurrent sequential requests. A second queue for completion queue events.
52 This model maps well to DMA and interrupt driven transfers. A request to do a
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/Zephyr-Core-3.5.0/dts/arm/st/g0/
Dstm32g050.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g050", "st,stm32g0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
25 compatible = "st,stm32-timers";
30 interrupt-names = "global";
35 dma1: dma@40020000 {
37 dma-requests = <7>;
41 dma-channels = <7>;
Dstm32g0b1.dtsi3 * Copyright (c) 2021 G-Technologies Sdn. Bhd.
5 * SPDX-License-Identifier: Apache-2.0
12 compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus";
15 clk_hsi48: clk-hsi48 {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
18 clock-frequency = <DT_FREQ_M(48)>;
23 pinctrl: pin-controller@50000000 {
25 compatible = "st,stm32-gpio";
26 gpio-controller;
[all …]
Dstm32g051.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g051", "st,stm32g0", "simple-bus";
14 compatible = "st,stm32-timers";
19 interrupt-names = "global";
23 compatible = "st,stm32-counter";
29 compatible = "st,stm32-timers";
34 interrupt-names = "global";
39 compatible = "st,stm32-counter";
45 compatible = "st,stm32-timers";
50 interrupt-names = "global";
[all …]
Dstm32g0b0.dtsi4 * SPDX-License-Identifier: Apache-2.0
11 compatible = "st,stm32g0b0", "st,stm32g0", "simple-bus";
13 pinctrl: pin-controller@50000000 {
15 compatible = "st,stm32-gpio";
16 gpio-controller;
17 #gpio-cells = <2>;
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-usart", "st,stm32-uart";
42 compatible = "st,stm32-timers";
47 interrupt-names = "global";
[all …]
Dstm32g070.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 compatible = "st,stm32g070", "st,stm32g0", "simple-bus";
15 compatible = "st,stm32-usart", "st,stm32-uart";
24 compatible = "st,stm32-usart", "st,stm32-uart";
33 compatible = "st,stm32-timers";
38 interrupt-names = "global";
43 compatible = "st,stm32-pwm";
45 #pwm-cells = <3>;
50 dma-requests= <53>;
Dstm32g071.dtsi6 * SPDX-License-Identifier: Apache-2.0
13 compatible = "st,stm32g071", "st,stm32g0", "simple-bus";
16 compatible = "st,stm32-usart", "st,stm32-uart";
25 compatible = "st,stm32-usart", "st,stm32-uart";
34 dma-requests= <57>;
38 compatible = "st,stm32-ucpd";
46 compatible = "st,stm32-ucpd";
/Zephyr-Core-3.5.0/drivers/serial/
Duart_mcux_flexcomm.c2 * Copyright (c) 2017, 2022-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
23 #include <zephyr/drivers/dma.h>
93 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_in()
94 uint32_t flags = USART_GetStatusFlags(config->base); in mcux_flexcomm_poll_in()
95 int ret = -1; in mcux_flexcomm_poll_in()
98 *c = USART_ReadByte(config->base); in mcux_flexcomm_poll_in()
108 const struct mcux_flexcomm_config *config = dev->config; in mcux_flexcomm_poll_out()
111 while (!(USART_GetStatusFlags(config->base) & kUSART_TxFifoEmptyFlag)) { in mcux_flexcomm_poll_out()
114 USART_WriteByte(config->base, c); in mcux_flexcomm_poll_out()
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/h7/
Dstm32h743.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h743", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h750.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h750", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
25 dma-requests= <107>;
29 dma-requests= <107>;
[all …]
Dstm32h745.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/display/panel.h>
12 compatible = "st,stm32h745", "st,stm32h7", "simple-bus";
14 flash-controller@52002000 {
16 compatible = "st,stm32-nv-flash", "soc-nv-flash";
17 write-block-size = <32>;
18 erase-block-size = <DT_SIZE_K(128)>;
20 max-erase-time = <4000>;
23 compatible = "st,stm32-nv-flash", "soc-nv-flash";
24 write-block-size = <32>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/mp1/
Dstm32mp157.dtsi5 * SPDX-License-Identifier: Apache-2.0
10 #include <arm/armv7-m.dtsi>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32_clock.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
15 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
16 #include <zephyr/dt-bindings/dma/stm32_dma.h>
17 #include <zephyr/dt-bindings/reset/stm32mp1_reset.h>
18 #include <zephyr/dt-bindings/display/panel.h>
[all …]
/Zephyr-Core-3.5.0/dts/arm/st/wb/
Dstm32wb.dtsi5 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/clock/stm32wb_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
13 #include <zephyr/dt-bindings/adc/adc.h>
14 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
15 #include <zephyr/dt-bindings/dma/stm32_dma.h>
16 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
[all …]

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