1# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32 DMA controller (V1)
6
7  It is present on stm32 devices like stm32F4 or stm32F2.
8  This DMA controller includes FIFO control registers.
9  DMA clients connected to the STM32 DMA controller must use the format
10  described in the dma.txt file, using a four-cell specifier for each
11  channel: a phandle to the DMA controller plus the following four integer cells:
12    1. channel: the dma stream from 0 to <dma-requests>
13    2. slot: DMA periph request ID, which is written in the DMAREQ_ID of the DMAMUX_CxCR
14    this value is 0 for Memory-to-memory transfers
15    or a value between <1> .. <dma-generators> (not supported yet)
16    or a value beweeen <dma-generators>+1  ..  <dma-generators>+<dma-requests>
17    3. channel-config: A 32bit mask specifying the DMA channel configuration
18    which is device dependent:
19        -bit 6-7 : Direction  (see dma.h)
20               0x0: MEM to MEM
21               0x1: MEM to PERIPH
22               0x2: PERIPH to MEM
23               0x3: reserved for PERIPH to PERIPH
24        -bit 9 : Peripheral Increment Address
25               0x0: no address increment between transfers
26               0x1: increment address between transfers
27        -bit 10 : Memory Increment Address
28               0x0: no address increment between transfers
29               0x1: increment address between transfers
30        -bit 11-12 : Peripheral data size
31               0x0: Byte (8 bits)
32               0x1: Half-word (16 bits)
33               0x2: Word (32 bits)
34               0x3: reserved
35        -bit 13-14 : Memory data size
36               0x0: Byte (8 bits)
37               0x1: Half-word (16 bits)
38               0x2: Word (32 bits)
39               0x3: reserved
40        -bit 15: Peripheral Increment Offset Size
41               0x0: offset size is linked to the peripheral bus width
42               0x1: offset size is fixed to 4 (32-bit alignment)
43        -bit 16-17 : Priority level
44               0x0: low
45               0x1: medium
46               0x2: high
47               0x3: very high
48    4. features: A 32bit bitfield value specifying DMA features
49        -bit 0-1: DMA FIFO threshold selection
50               0x0: 1/4 full FIFO
51               0x1: 1/2 full FIFO
52               0x2: 3/4 full FIFO
53               0x3: full FIFO
54
55    examples for stm32f411
56     dma2: dma-controller@40020400 {
57         compatible = "st,stm32-dma-v1";
58         ...
59         st,mem2mem;
60         dma-requests = <7>;
61         status = "disabled";
62        };
63
64  For the client part, example for stm32f411 on DMA2 instance
65    Tx using stream 5 on channel 3 (stream 2 on channel 2 is also possible)
66    Rx using stream 2 on channel 3 (stream 0 on channel 3 is also possible)
67    spi1 {
68     dmas = <&dma2 5 3 0x28440 0x03>,
69           <&dma2 2 3 0x28480 0x03>;
70     dma-names = "tx", "rx";
71     };
72
73compatible: "st,stm32-dma-v1"
74
75include: st,stm32-dma.yaml
76
77properties:
78  "#dma-cells":
79    const: 4
80
81# Parameter syntax of stm32 follows the dma client dts syntax
82# in the Linux kernel declared in
83# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
84
85dma-cells:
86  - channel
87  - slot
88  - channel-config
89  - features
90