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24 #define __PLATFORM_BASE_ADDRESS_H__28 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */29 #define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */30 #define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */31 #define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */32 #define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */33 #define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */34 #define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */35 #define ISRAM1_BASE_NS 0x21100000 /* Internal SRAM Area Non-Secure base address */36 #define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */[all …]
18 #define __DEVICE_CFG_H__33 #define MPS3_IO_S34 #define MPS3_IO_DEV MPS3_IO_DEV_S37 #define I2C0_SBCON_S38 #define I2C0_SBCON_DEV I2C0_SBCON_DEV_S41 #define MPS3_I2S_S42 #define MPS3_I2S_DEV MPS3_I2S_DEV_S45 #define UART0_CMSDK_S46 #define UART0_CMSDK_DEV UART0_CMSDK_DEV_S47 #define UART1_CMSDK_S[all …]
18 #define __RTE_DEVICE_H22 #define RTE_USART0 126 #define RTE_USART1 130 #define RTE_ISRAM0_MPC 134 #define RTE_ISRAM1_MPC 138 #define RTE_SRAM_MPC 142 #define RTE_QSPI_MPC 146 #define RTE_PPC_SSE300_MAIN0 150 #define RTE_PPC_SSE300_MAIN_EXP0 154 #define RTE_PPC_SSE300_MAIN_EXP1 1[all …]
23 #define __PLATFORM_BASE_ADDRESS_H__27 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */28 #define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */29 #define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */30 #define DTCM1_BASE_NS 0x20002000 /* Data TCM block 1 Non-Secure base address */31 #define DTCM2_BASE_NS 0x20004000 /* Data TCM block 2 Non-Secure base address */32 #define DTCM3_BASE_NS 0x20006000 /* Data TCM block 3 Non-Secure base address */33 #define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */34 #define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */35 #define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */[all …]
18 #define __RTE_DEVICE_H22 #define RTE_USART0 126 #define RTE_USART1 130 #define RTE_ISRAM0_MPC 034 #define RTE_ISRAM1_MPC 038 #define RTE_SRAM_MPC 042 #define RTE_QSPI_MPC 046 #define RTE_PPC_CORSTONE310_MAIN0 050 #define RTE_PPC_CORSTONE310_MAIN_EXP0 054 #define RTE_PPC_CORSTONE310_MAIN_EXP1 0[all …]
2 #define REGIONS_SSE_310_MPS3_H20 #define __RAM0_BASE 0x0000000024 #define __RAM0_SIZE 0x0000800027 #define __RAM0_DEFAULT 130 #define __RAM0_NOINIT 037 #define __RAM1_BASE 0x0100000041 #define __RAM1_SIZE 0x0020000044 #define __RAM1_DEFAULT 147 #define __RAM1_NOINIT 054 #define __RAM2_BASE 0x20000000[all …]
18 #define __REGION_DEFS_H__32 #define S_CODE_START ( S_ROM_ALIAS )33 #define S_CODE_SIZE ( TOTAL_S_ROM_SIZE )34 #define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE )36 #define S_DATA_START ( S_RAM_ALIAS )37 #define S_DATA_SIZE ( TOTAL_S_RAM_SIZE )38 #define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE )41 #define NS_CODE_START ( NS_ROM_ALIAS )42 #define NS_CODE_SIZE ( TOTAL_NS_ROM_SIZE )43 #define NS_CODE_LIMIT ( NS_CODE_START + NS_CODE_SIZE )[all …]
24 #define __PLATFORM_BASE_ADDRESS_H__28 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */29 #define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */30 #define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */31 #define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */32 #define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */33 #define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */34 #define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */35 #define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */36 #define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */[all …]
18 #define __DEVICE_CFG_H__33 #define MPS3_IO_S34 #define MPS3_IO_DEV MPS3_IO_DEV_S37 //#define I2C0_SBCON_S38 #define I2C0_SBCON_DEV I2C0_SBCON_DEV_S41 #define MPS3_I2S_S42 #define MPS3_I2S_DEV MPS3_I2S_DEV_S45 #define UART0_CMSDK_S46 #define UART0_CMSDK_DEV UART0_CMSDK_DEV_S47 #define UART1_CMSDK_S[all …]
18 #define __RTE_DEVICE_H22 #define RTE_USART0 126 #define RTE_USART1 130 #define RTE_ISRAM0_MPC 034 #define RTE_ISRAM1_MPC 038 #define RTE_SRAM_MPC 042 #define RTE_QSPI_MPC 046 #define RTE_PPC_SSE300_MAIN0 050 #define RTE_PPC_SSE300_MAIN_EXP0 054 #define RTE_PPC_SSE300_MAIN_EXP1 0[all …]
24 #define GCC_COMPILER44 #define __STATIC_FORCEINLINE static __forceinline45 #define __STATIC_INLINE static __inline46 #define __ALIGNED(x) __declspec(align(x))47 #define __WEAK50 #define __ALIGNED(x) __attribute__((aligned(x)))51 #define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) 52 #define __STATIC_INLINE static inline53 #define __WEAK56 #define __ALIGNED(x) __attribute__((aligned(x)))[all …]
2 #define REGIONS_V2M_MPS3_SSE_300_FVP_H20 #define __RAM0_BASE 0x1000000024 #define __RAM0_SIZE 0x0020000027 #define __RAM0_DEFAULT 130 #define __RAM0_NOINIT 037 #define __RAM1_BASE 0x0000000041 #define __RAM1_SIZE 0x0020000044 #define __RAM1_DEFAULT 047 #define __RAM1_NOINIT 054 #define __RAM2_BASE 0x30000000[all …]
28 #define ARM_MATH_TYPES_H_35 #define ARM_DSP_ATTRIBUTE 39 #define ARM_DSP_TABLE_ATTRIBUTE 67 #define ARM_DSP_BUILT_WITH_GCC 87 #define __STATIC_FORCEINLINE static __forceinline88 #define __STATIC_INLINE static __inline89 #define __ALIGNED(x) __declspec(align(x))90 #define __WEAK93 #define __ALIGNED(x) __attribute__((aligned(x)))94 #define __STATIC_FORCEINLINE static inline __attribute__((always_inline)) [all …]
30 #define ARM_COMMON_TABLES_H78 #define twiddleCoef twiddleCoef_4096153 #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)156 #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)159 #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)162 #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)165 #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)168 #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)171 #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)174 #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)[all …]
2 #define REGIONS_SSE_300_MPS3_H20 #define __RAM0_BASE 0x0000000024 #define __RAM0_SIZE 0x0008000027 #define __RAM0_DEFAULT 130 #define __RAM0_NOINIT 037 #define __RAM1_BASE 0x0100000041 #define __RAM1_SIZE 0x0010000044 #define __RAM1_DEFAULT 147 #define __RAM1_NOINIT 054 #define __RAM2_BASE 0x20000000[all …]
2 #define _MFCC_DATA_H_ 20 #define NB_MFCC_DCT_COEFS_CONFIG1_F32 26025 #define NB_MFCC_DCT_COEFS_CONFIG1_Q31 26030 #define NB_MFCC_DCT_COEFS_CONFIG1_Q15 26042 #define NB_MFCC_WIN_COEFS_CONFIG1_F32 102447 #define NB_MFCC_WIN_COEFS_CONFIG1_Q31 102452 #define NB_MFCC_WIN_COEFS_CONFIG1_Q15 102457 #define NB_MFCC_WIN_COEFS_CONFIG2_F32 51262 #define NB_MFCC_WIN_COEFS_CONFIG2_Q31 51267 #define NB_MFCC_WIN_COEFS_CONFIG2_Q15 512[all …]
