Lines Matching full:define

18 #define __DEVICE_CFG_H__
33 #define MPS3_IO_S
34 #define MPS3_IO_DEV                 MPS3_IO_DEV_S
37 #define I2C0_SBCON_S
38 #define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
41 #define MPS3_I2S_S
42 #define MPS3_I2S_DEV                MPS3_I2S_DEV_S
45 #define UART0_CMSDK_S
46 #define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
47 #define UART1_CMSDK_S
48 #define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
50 #define DEFAULT_UART_BAUDRATE    115200U
53 #define MPC_ISRAM0_S
54 #define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
56 #define MPC_ISRAM1_S
57 #define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
59 #define MPC_SRAM_S
60 #define MPC_SRAM_DEV                MPC_SRAM_DEV_S
62 #define MPC_QSPI_S
63 #define MPC_QSPI_DEV                MPC_QSPI_DEV_S
66 #define SYSCOUNTER_CNTRL_ARMV8_M_S
67 #define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
69 #define SYSCOUNTER_READ_ARMV8_M_S
70 #define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
74 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
75 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
76 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
77 #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
80 #define SYSTIMER0_ARMV8_M_S
81 #define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
82 #define SYSTIMER1_ARMV8_M_S
83 #define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
84 #define SYSTIMER2_ARMV8_M_S
85 #define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
86 #define SYSTIMER3_ARMV8_M_S
87 #define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
89 #define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
90 #define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
91 #define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
92 #define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
95 #define GPIO0_CMSDK_S
96 #define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
97 #define GPIO1_CMSDK_S
98 #define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
99 #define GPIO2_CMSDK_S
100 #define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
101 #define GPIO3_CMSDK_S
102 #define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
105 #define SYSWDOG_ARMV8_M_S
106 #define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
109 #define MPC_VM0_S
110 #define MPC_VM0_DEV MPC_VM0_DEV_S
111 #define MPC_VM1_S
112 #define MPC_VM1_DEV MPC_VM1_DEV_S
113 #define MPC_SSRAM2_S
114 #define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
115 #define MPC_SSRAM3_S
116 #define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
119 #define PPC_SSE300_MAIN0_S
120 #define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
121 #define PPC_SSE300_MAIN_EXP0_S
122 #define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
123 #define PPC_SSE300_MAIN_EXP1_S
124 #define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
125 #define PPC_SSE300_MAIN_EXP2_S
126 #define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
127 #define PPC_SSE300_MAIN_EXP3_S
128 #define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
129 #define PPC_SSE300_PERIPH0_S
130 #define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
131 #define PPC_SSE300_PERIPH1_S
132 #define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
133 #define PPC_SSE300_PERIPH_EXP0_S
134 #define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
135 #define PPC_SSE300_PERIPH_EXP1_S
136 #define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
137 #define PPC_SSE300_PERIPH_EXP2_S
138 #define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
139 #define PPC_SSE300_PERIPH_EXP3_S
140 #define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
144 #define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
145 #define SPI1_PL022_S
146 #define SPI1_PL022_DEV SPI1_PL022_DEV_S