1/*
2 * Copyright (c) 2020-2022 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *     http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing software
11 * distributed under the License is distributed on an "AS IS" BASIS
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#ifndef __DEVICE_CFG_H__
18#define __DEVICE_CFG_H__
19
20/**
21 * \file device_cfg.h
22 * \brief Configuration file native driver re-targeting
23 *
24 * \details This file can be used to add native driver specific macro
25 *          definitions to select which peripherals are available in the build.
26 *
27 * This is a default device configuration file with all peripherals enabled.
28 */
29
30/* Secure only peripheral configuration */
31
32/* ARM MPS3 IO SCC */
33#define MPS3_IO_S
34#define MPS3_IO_DEV                 MPS3_IO_DEV_S
35
36/* I2C_SBCon */
37#define I2C0_SBCON_S
38#define I2C0_SBCON_DEV              I2C0_SBCON_DEV_S
39
40/* I2S */
41#define MPS3_I2S_S
42#define MPS3_I2S_DEV                MPS3_I2S_DEV_S
43
44/* ARM UART Controller PL011 */
45#define UART0_CMSDK_S
46#define UART0_CMSDK_DEV          UART0_CMSDK_DEV_S
47#define UART1_CMSDK_S
48#define UART1_CMSDK_DEV          UART1_CMSDK_DEV_S
49
50#define DEFAULT_UART_BAUDRATE    115200U
51
52/* To be used as CODE and DATA sram */
53#define MPC_ISRAM0_S
54#define MPC_ISRAM0_DEV              MPC_ISRAM0_DEV_S
55
56#define MPC_ISRAM1_S
57#define MPC_ISRAM1_DEV              MPC_ISRAM0_DEV_S
58
59#define MPC_SRAM_S
60#define MPC_SRAM_DEV                MPC_SRAM_DEV_S
61
62#define MPC_QSPI_S
63#define MPC_QSPI_DEV                MPC_QSPI_DEV_S
64
65/** System Counter Armv8-M */
66#define SYSCOUNTER_CNTRL_ARMV8_M_S
67#define SYSCOUNTER_CNTRL_ARMV8_M_DEV    SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
68
69#define SYSCOUNTER_READ_ARMV8_M_S
70#define SYSCOUNTER_READ_ARMV8_M_DEV     SYSCOUNTER_READ_ARMV8_M_DEV_S
71/**
72 * Arbitrary scaling values for test purposes
73 */
74#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT           1u
75#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT         0u
76#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT           1u
77#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT         0u
78
79/* System timer */
80#define SYSTIMER0_ARMV8_M_S
81#define SYSTIMER0_ARMV8_M_DEV    SYSTIMER0_ARMV8_M_DEV_S
82#define SYSTIMER1_ARMV8_M_S
83#define SYSTIMER1_ARMV8_M_DEV    SYSTIMER1_ARMV8_M_DEV_S
84#define SYSTIMER2_ARMV8_M_S
85#define SYSTIMER2_ARMV8_M_DEV    SYSTIMER2_ARMV8_M_DEV_S
86#define SYSTIMER3_ARMV8_M_S
87#define SYSTIMER3_ARMV8_M_DEV    SYSTIMER3_ARMV8_M_DEV_S
88
89#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
90#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
91#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
92#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    (25000000ul)
93
94/* CMSDK GPIO driver structures */
95#define GPIO0_CMSDK_S
96#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S
97#define GPIO1_CMSDK_S
98#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S
99#define GPIO2_CMSDK_S
100#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S
101#define GPIO3_CMSDK_S
102#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S
103
104/* System Watchdogs */
105#define SYSWDOG_ARMV8_M_S
106#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S
107
108/* ARM MPC SIE 300 driver structures */
109#define MPC_VM0_S
110#define MPC_VM0_DEV MPC_VM0_DEV_S
111#define MPC_VM1_S
112#define MPC_VM1_DEV MPC_VM1_DEV_S
113#define MPC_SSRAM2_S
114#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S
115#define MPC_SSRAM3_S
116#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S
117
118/* ARM PPC driver structures */
119#define PPC_SSE300_MAIN0_S
120#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S
121#define PPC_SSE300_MAIN_EXP0_S
122#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S
123#define PPC_SSE300_MAIN_EXP1_S
124#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S
125#define PPC_SSE300_MAIN_EXP2_S
126#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S
127#define PPC_SSE300_MAIN_EXP3_S
128#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S
129#define PPC_SSE300_PERIPH0_S
130#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S
131#define PPC_SSE300_PERIPH1_S
132#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S
133#define PPC_SSE300_PERIPH_EXP0_S
134#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S
135#define PPC_SSE300_PERIPH_EXP1_S
136#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S
137#define PPC_SSE300_PERIPH_EXP2_S
138#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S
139#define PPC_SSE300_PERIPH_EXP3_S
140#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S
141
142/* ARM SPI PL022 */
143/* Invalid device stubs are not defined */
144#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
145#define SPI1_PL022_S
146#define SPI1_PL022_DEV SPI1_PL022_DEV_S
147
148
149#endif  /* __DEVICE_CFG_H__ */
150