Searched full:debug (Results 1 – 25 of 106) sorted by relevance
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3 …dized access to the CoreSight Debug Access Port ([DAP](https://developer.arm.com/documentation/102…4 …rocessors as part of the [CoreSight Debug and Trace](https://developer.arm.com/ip-products/system-…10 …Debug Access Port (DAP) typically either with a 5-pin JTAG or with a 2-pin Serial Wired Debug (SWD…12 …debug unit that implements the communication between the debug port of the device and USB port. Wi…23 - Connects via 5-pin JTAG or 2-pin Serial Wire Debug (SWD).26 - Easy to deploy to debug units based on Cortex-M microcontrollers.27 - Debug unit may be integrated on an evaluation board.30 - Supports Test Domain Timer for time measurement using the debug unit.
1 /* ##################################### Debug In/Output function ############################### */17 \brief **[Deprecated]** Structure type to access the Core Debug Register.22 …__IOM uint32_t DHCSR; ///< Offset: 0x000 (R/W) Debug Halting Control and Status …23 …__OM uint32_t DCRSR; ///< Offset: 0x004 ( /W) Debug Core Register Selector Regi…24 __IOM uint32_t DCRDR; ///< Offset: 0x008 (R/W) Debug Core Register Data Register25 …__IOM uint32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Contr…26 …__OM uint32_t DSCEMCR; ///< Offset: 0x010 ( /W) Debug Set Clear Exception and Mon…27 …__IOM uint32_t DAUTHCTRL; ///< Offset: 0x014 (R/W) Debug Authentication Control Regi…28 …__IOM uint32_t DSCSR; ///< Offset: 0x018 (R/W) Debug Security Control and Status…33 \brief **[Deprecated]** Core Debug configuration structure
1 /* ##################################### Debug In/Output function ############################### */3 \defgroup ITM_Debug_gr Debug Access4 \brief Debug Access to the Instrumented Trace Macrocell (ITM)6 CMSIS provides additional debug functions to enlarge the Debug Access. 15 which can be used for printf-style output via the debug interface.30 A debugger may support a <b>Debug (printf) Viewer</b> window to display data.34 <b>Debug (printf) Viewer</b> window.38 - Read the character from the <b>Debug (printf) Viewer</b> window.
124 __IOM uint32_t DFSR; ///< Offset: 0x030 (R/W) Debug Fault Status Register129 __IM uint32_t ID_DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register250 \brief Structure type to access the Debug Control Block Registers (DCB).254 …__IOM uint32_t DHCSR; ///< Offset: 0x000 (R/W) Debug Halting Control and Status …255 …__OM uint32_t DCRSR; ///< Offset: 0x004 ( /W) Debug Core Register Selector Regi…256 __IOM uint32_t DCRDR; ///< Offset: 0x008 (R/W) Debug Core Register Data Register257 …__IOM uint32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Contr…258 …__OM uint32_t DSCEMCR; ///< Offset: 0x010 ( /W) Debug Set Clear Exception and Mon…259 …__IOM uint32_t DAUTHCTRL; ///< Offset: 0x014 (R/W) Debug Authentication Control Regi…260 …__IOM uint32_t DSCSR; ///< Offset: 0x018 (R/W) Debug Security Control and Status…[all …]
189 \li for automatic generation of peripheral register debug information.215 - Core Debug Register1012 \defgroup CMSIS_DCB Debug Control Block1013 \brief Type definitions for the Debug Control Block Registers1018 \brief Structure type to access the Debug Control Block Registers (DCB).1022 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1023 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…1024 …__IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register…1025 …__IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Contr…1027 …__IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Regi…[all …]
292 \li for automatic generation of peripheral register debug information.318 - Core Debug Register533 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */538 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */841 /** \brief SCB Debug Fault Status Register Definitions */1778 \defgroup CMSIS_DCB Debug Control Block1779 \brief Type definitions for the Debug Control Block Registers1784 \brief Structure type to access the Debug Control Block Registers (DCB).1788 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1789 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
303 \li for automatic generation of peripheral register debug information.329 - Core Debug Register544 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */549 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */860 /** \brief SCB Debug Fault Status Register Definitions */1929 \defgroup CMSIS_DCB Debug Control Block1930 \brief Type definitions for the Debug Control Block Registers1935 \brief Structure type to access the Debug Control Block Registers (DCB).1939 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1940 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
299 \li for automatic generation of peripheral register debug information.327 - Core Debug Register543 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */548 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */861 /** \brief SCB Debug Fault Status Register Definitions */911 /** \brief SCB Debug Feature Register 0 Definitions */1533 …__IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power Stat…1546 /** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */2875 … /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */2876 …0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */[all …]
299 \li for automatic generation of peripheral register debug information.327 - Core Debug Register564 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */569 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */882 /** \brief SCB Debug Fault Status Register Definitions */932 /** \brief SCB Debug Feature Register 0 Definitions */1527 …__IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power Stat…1540 /** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */2899 … /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */2900 …0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */[all …]
304 \li for automatic generation of peripheral register debug information.332 - Core Debug Register569 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */574 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */887 /** \brief SCB Debug Fault Status Register Definitions */937 /** \brief SCB Debug Feature Register 0 Definitions */1580 …__IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power Stat…1590 /** \brief PwrModCtl Debug Power Domain Low Power State Register Definitions */2912 … /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */2913 …0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */[all …]
168 \li for automatic generation of peripheral register debug information.194 - Core Debug Register392 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */397 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */634 /** \brief SCB Debug Fault Status Register Definitions */1233 \defgroup CMSIS_DCB Debug Control Block1234 \brief Type definitions for the Debug Control Block Registers1239 \brief Structure type to access the Debug Control Block Registers (DCB).1243 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1244 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
168 \li for automatic generation of peripheral register debug information.194 - Core Debug Register392 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */397 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */629 /** \brief SCB Debug Fault Status Register Definitions */1216 \defgroup CMSIS_DCB Debug Control Block1217 \brief Type definitions for the Debug Control Block Registers1222 \brief Structure type to access the Debug Control Block Registers (DCB).1226 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1227 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
227 \li for automatic generation of peripheral register debug information.253 - Core Debug Register465 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */470 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */705 /** \brief SCB Debug Fault Status Register Definitions */1409 \defgroup CMSIS_DCB Debug Control Block1410 \brief Type definitions for the Debug Control Block Registers1415 \brief Structure type to access the Debug Control Block Registers (DCB).1419 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1420 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
242 \li for automatic generation of peripheral register debug information.268 - Core Debug Register480 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */485 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */757 /** \brief SCB Debug Fault Status Register Definitions */1631 \defgroup CMSIS_DCB Debug Control Block1632 \brief Type definitions for the Debug Control Block Registers1637 \brief Structure type to access the Debug Control Block Registers (DCB).1641 …__IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status …1642 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…[all …]
134 debug: on138 debug: on142 debug: on146 debug: on
25 \brief Close the debug session.27 Debug session dead end - debug script should close session here.51 -# Debug session ends in dead loop74 closeDebug(); /* Close debug session */ in ts_cmsis_cv()
22 - Works on all Cortex-M devices with only simple debug adapters necessary.26 - Enables RTOS-aware debug for CMSIS-RTX and CMSIS-FreeRTOS.28 …Vision IDE](https://developer.arm.com/documentation/101407/0538/Debugging/Debug-Windows-and-Dialog…
3 …learning curve for microcontroller developers, speed-up project build and debug, and thus reduce t…60 …h2">CMSIS-DAP</span><span class="tiletxt">Firmware for debug units interfacing to CoreSight Debug …76 …IS-SVD</span><span class="tiletxt">Peripheral description of a device for debug view</span><span c…86 …- It provides interfaces for debug connectivity, debug peripheral views, software delivery, and de…
317 /* DWARF debug sections.321 .debug 0 : { *(.debug) }
