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/Zephyr-Core-2.7.6/drivers/usb/device/
DKconfig7 bool "Enable USB device controller drivers"
9 Enable USB device controller drivers.
14 bool "Designware USB Device Controller Driver"
16 Designware USB Device Controller Driver.
19 bool "DesignWare Controller and PHY support for USB specification 2.0"
25 bool "USB device controller driver for STM32 devices"
42 bool "SAM0 series USB Device Controller driver"
46 SAM0 family USB device controller Driver.
51 bool "SAM4L USBC Device Controller driver"
55 SAM4L family USBC device controller Driver.
[all …]
/Zephyr-Core-2.7.6/dts/arm/cypress/
Dpsoc6_cm0.dtsi30 intmux_ch0: interrupt-controller@0 {
34 interrupt-controller;
39 intmux_ch1: interrupt-controller@1 {
43 interrupt-controller;
48 intmux_ch2: interrupt-controller@2 {
52 interrupt-controller;
57 intmux_ch3: interrupt-controller@3 {
61 interrupt-controller;
66 intmux_ch4: interrupt-controller@4 {
70 interrupt-controller;
[all …]
/Zephyr-Core-2.7.6/subsys/bluetooth/controller/
DKconfig1 # Bluetooth Controller configuration options
6 comment "BLE Controller support"
8 # The following symbols are enabled depending if the controller actually
85 bool "Bluetooth Controller"
87 Enables support for SoC native controller implementations.
107 comment "BLE Controller configuration"
110 bool "Enable crypto functions in Controller"
115 provided by the controller.
182 Set the number of Rx PDUs to be buffered in the controller. In a 7.5ms
193 in the controller.
[all …]
DKconfig.df1 # Zephyr Bluetooth Controller configuration options
40 # Basic controller functionalities required for implementation of
49 controller.
93 Enable support for reception of Constant Tone Extension in controller.
100 in controller.
107 in controller.
116 feature in controller.
124 in controller.
141 Defines maximum length of antenna switch pattern that controller
183 implementation in controller.
DKconfig.ll_sw_split1 # Zephyr Bluetooth Controller configuration options
78 # Controller's Co-Operative high priority Rx thread stack size.
86 Enable use of settings system in controller.
92 Make the controller's Company Id and Subversion Number configurable
96 hex "Controller Company Id"
103 Company Identifier for the controller. The full list of Bluetooth
117 Makes advanced features visible to controller developers.
123 bool "LE Controller-based Software Privacy"
129 int "LE Controller-based Software Privacy Resolving List size"
135 Controller-based Software deferred Privacy.
[all …]
/Zephyr-Core-2.7.6/drivers/interrupt_controller/
DKconfig.dw5 bool "Designware Interrupt Controller"
8 Designware Interrupt Controller can be used as a 2nd level interrupt
9 controller which combines several sources of interrupt into one line
10 that is then routed to the 1st level interrupt controller.
15 string "Name for Designware Interrupt Controller"
18 Give a name for the instance of Designware Interrupt Controller
31 the ISRs for Designware Interrupt Controller are assigned.
34 int "Init priority for DW interrupt controller"
37 DesignWare Interrupt Controller initialization priority.
DKconfig1 # interrupt controller configuration options
20 bool "Platform Level Interrupt Controller (PLIC)"
26 Platform Level Interrupt Controller provides support
30 bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
33 Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
36 bool "VexRiscv LiteX Interrupt controller"
42 bool "GRLIB IRQMP interrupt controller"
/Zephyr-Core-2.7.6/subsys/bluetooth/common/
DKconfig13 Controller. This value does not include the HCI ACL header.
14 The Host will segment the data transmitted to the Controller so that
15 packets sent to the Controller will contain data up to this size.
17 Controller.
19 by the Controller and use the smallest value supported by both the
20 Bost and the Controller.
23 The Controller will return this value in the HCI LE Read Buffer
25 Layer transmission size then the Controller will perform
39 Controller. This determines the maximum amount of data packets the
40 Host can have queued in the Controller before waiting for the
[all …]
/Zephyr-Core-2.7.6/dts/riscv/
Dvirt.dtsi48 hlic0: interrupt-controller {
50 interrupt-controller;
61 hlic1: interrupt-controller {
63 interrupt-controller;
74 hlic2: interrupt-controller {
76 interrupt-controller;
87 hlic3: interrupt-controller {
89 interrupt-controller;
100 hlic4: interrupt-controller {
102 interrupt-controller;
[all …]
Drv32m1.dtsi6 #include <dt-bindings/interrupt-controller/openisa-intmux.h>
16 zephyr,flash-controller = &ftfe;
51 pcc0: clock-controller@4002b000 {
58 pcc1: clock-controller@41027000 {
65 event0: interrupt-controller@e0041000 {
68 interrupt-controller;
72 event1: interrupt-controller@4101f000 {
75 interrupt-controller;
90 intmux0_ch0: interrupt-controller@0 {
93 interrupt-controller;
[all …]
/Zephyr-Core-2.7.6/samples/bluetooth/hci_uart/
DREADME.rst9 Expose the Zephyr Bluetooth controller support over UART to another device/CPU
20 By default the controller builds use the following settings:
32 Using the controller with emulators and BlueZ
36 controller and expose it to Linux's BlueZ. This can be very useful for testing
37 the Zephyr Link Layer with the BlueZ Host. The Zephyr BLE controller can also
38 provide a modern BLE 5.0 controller to a Linux-based machine for native
58 Using the controller with QEMU and Native POSIX
61 In order to use the HCI UART controller with QEMU or Native POSIX you will need
71 ``/dev/ttyACM0`` string to point to the serial device your controller is
80 interacting with the controller and instead just be aware of it in order
[all …]
/Zephyr-Core-2.7.6/modules/
DKconfig.stm3230 Enable STM32Cube Controller Area Network (CAN) HAL module driver
35 Enable STM32Cube HDMI-CEC controller (CEC) HAL module driver
108 Enable STM32Cube Direct Memory Access controller (DMA) HAL module
114 Enable STM32Cube Chrom-Art Accelerator™ controller (DMA2D) HAL module
120 Enable STM32Cube Extended Direct Memory Access controller (DMA) HAL
141 Enable STM32Cube Extended interrupt and event controller (EXTI) HAL
147 Enable STM32Cube Controller area network with flexible data rate
218 Enable STM32Cube Host Controller device (HCD) HAL module driver
255 Enable STM32Cube Inter-Processor communication controller (IPCC) HAL
276 Enable STM32Cube LCD controller (LCD) HAL module driver
[all …]
/Zephyr-Core-2.7.6/drivers/i2c/
Di2c_npcx_controller.h17 * @brief Lock the mutex of npcx i2c controller.
19 * @param i2c_dev Pointer to the device structure for i2c controller instance.
24 * @brief Unlock the mutex of npcx i2c controller.
26 * @param i2c_dev Pointer to the device structure for i2c controller instance.
31 * @brief Configure operation of a npcx i2c controller.
33 * @param i2c_dev Pointer to the device structure for i2c controller instance.
35 * for the I2C controller.
45 * @brief Perform data transfer to via npcx i2c controller.
47 * @param i2c_dev Pointer to the device structure for i2c controller instance.
/Zephyr-Core-2.7.6/scripts/dts/python-devicetree/tests/
Dtest.dts17 controller {
20 interrupt-controller;
25 interrupt-parent = <&{/interrupt-parent-test/controller}>;
29 controller-0 {
32 interrupt-controller;
34 controller-1 {
37 interrupt-controller;
39 controller-2 {
42 interrupt-controller;
46 &{/interrupts-extended-test/controller-0} 1
[all …]
/Zephyr-Core-2.7.6/dts/bindings/memory-controllers/
Dst,stm32-fmc.yaml5 STM32 Flexible Memory Controller (FMC).
11 controller. Each external device is accessed by means of a unique chip select.
14 The flexible memory controller includes three memory controllers:
16 - NOR/PSRAM memory controller
17 - NAND memory controller (some devices also support PC Card)
18 - Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
20 Each memory controller is defined below the FMC DeviceTree node and is managed
/Zephyr-Core-2.7.6/drivers/syscon/
DKconfig10 bool "SYSCON (System Controller) drivers"
12 SYSCON (System Controller) drivers. System controller node represents
28 bool "Generic SYSCON (System Controller) driver"
31 Enable generic SYSCON (System Controller) driver
34 int "SYSCON (System Controller) driver init priority"
/Zephyr-Core-2.7.6/tests/bluetooth/df/connectionless_cte_chains/
DCMakeLists.txt15 # Include paths to allow access to functions implemented in BLE controller
19 ${ZEPHYR_BASE}/subsys/bluetooth/controller)
21 ${ZEPHYR_BASE}/subsys/bluetooth/controller/include)
23 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw)
25 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic)
27 ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic/lll)
/Zephyr-Core-2.7.6/samples/drivers/can/
DREADME.rst3 Controller Area Network
9 This sample demonstrates how to use the Controller Area Network (CAN) API.
23 integrated CAN controller or for boards with a SoC that has been augmented
24 with a stand alone CAN controller.
26 Integrated CAN controller
36 Stand alone CAN controller
40 provides the MCP2515 CAN controller:
/Zephyr-Core-2.7.6/include/devicetree/
Dclocks.h26 * @brief Get the node identifier for the controller phandle from a
31 * clk1: clock-controller@... { ... };
33 * clk2: clock-controller@... { ... };
46 * @return the node identifier for the clock controller referenced at
56 * @return a node identifier for the clocks controller at index 0
63 * @brief Get the node identifier for the controller phandle from a
69 * clk1: clock-controller@... { ... };
71 * clk2: clock-controller@... { ... };
85 * @return the node identifier for the clock controller referenced by name
95 * It's an error if the clock controller node referenced by the
[all …]
/Zephyr-Core-2.7.6/doc/guides/bluetooth/
Dbluetooth-arch.rst30 * **Controller**: The Controller implements the Link Layer (LE LL), the
41 Host Controller Interface
45 communicate with a Controller. This is called the Host Controller Interface
48 can send to a Controller and the events that it can expect in return, and also
50 ensures that different Host and Controller implementations can communicate
60 it possible to implement the Host and Controller on different platforms. The two
66 Controller communicate directly through function calls and queues in RAM. The
73 one running the Application and the Host, and a second one with the Controller
76 Hosts when using the Zephyr OS as a Controller. Since HCI ensures
77 interoperability among Host and Controller implementations, including of course
[all …]
/Zephyr-Core-2.7.6/drivers/memc/
DKconfig.stm327 bool "Enable STM32 Flexible Memory Controller (FMC)"
10 Enable STM32 Flexible Memory Controller.
15 bool "Enable STM32 FMC SDRAM controller"
21 Enable STM32 FMC SDRAM controller.
/Zephyr-Core-2.7.6/subsys/bluetooth/
DKconfig31 HCI-based stack with optional host & controller parts and an
52 This option allows to access Bluetooth controller
138 bool "Controller to Host ACL flow control support"
141 # Enable if building a Controller-only build
145 Enable support for throttling ACL buffers from the controller
147 controller are on separate cores since it ensures that we do
152 # Enable if building a Controller-only build
155 Enable this to get access to the remote version in the Controller and
175 rsource "controller/Kconfig"
188 can set their own. Note that the controller's Company Identifier is
/Zephyr-Core-2.7.6/drivers/display/
DKconfig.ssd13061 # SSD1306 display controller configuration options
22 prompt "Display controller type"
25 Specify the type of the controller.
28 bool "Default SSD1306 controller"
/Zephyr-Core-2.7.6/tests/drivers/i2c/i2c_slave_api/
DREADME.txt12 Zephyr application issues commands to one controller that are responded
13 to by the simulated EEPROM connected through the other controller.
28 * Issue commands on one bus controller (operating as the bus master) and
29 verify that the data supplied by the other controller (slave) match
34 Transfer of commands from one bus controller to the other is
40 or the controller driver has bugs, the test will fail one or more I2C
/Zephyr-Core-2.7.6/dts/bindings/dma/
Dst,stm32-dma.yaml5 STM32 DMA controller
7 The STM32 DMA is a general-purpose direct memory access controller
11 or V2 like stm32L4 soc or stm322WB, some also have DMAMUX controller
16 include: dma-controller.yaml
28 description: If the DMA controller V1 supports memory to memory transfer

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