1/*
2 * Copyright (c) 2020 Cobham Gaisler AB
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/*
8 * This file is based on:
9 *   qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
10 *   dtc virt.dtb > virt.dtsi
11 */
12
13/dts-v1/;
14
15/ {
16	#address-cells = < 0x01 >;
17	#size-cells = < 0x01 >;
18	compatible = "riscv-virtio";
19	model = "riscv-virtio,qemu";
20
21	flash@20000000 {
22		bank-width = < 0x04 >;
23		reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
24		compatible = "cfi-flash";
25	};
26
27	uart0: uart@10000000 {
28		interrupts = < 0x0a 1 >;
29		interrupt-parent = < &plic >;
30		clock-frequency = < 0x384000 >;
31		reg = < 0x10000000 0x100 >;
32		compatible = "ns16550";
33		reg-shift = < 0 >;
34		label = "UART_0";
35	};
36
37	cpus {
38		#address-cells = < 0x01 >;
39		#size-cells = < 0x00 >;
40		timebase-frequency = < 10000000 >;
41
42		cpu@0 {
43			device_type = "cpu";
44			reg = < 0x00 >;
45			status = "okay";
46			compatible = "riscv";
47
48			hlic0: interrupt-controller {
49				#interrupt-cells = < 0x01 >;
50				interrupt-controller;
51				compatible = "riscv,cpu-intc";
52			};
53		};
54
55		cpu@1 {
56			device_type = "cpu";
57			reg = < 0x01 >;
58			status = "okay";
59			compatible = "riscv";
60
61			hlic1: interrupt-controller {
62				#interrupt-cells = < 0x01 >;
63				interrupt-controller;
64				compatible = "riscv,cpu-intc";
65			};
66		};
67
68		cpu@2 {
69			device_type = "cpu";
70			reg = < 0x02 >;
71			status = "okay";
72			compatible = "riscv";
73
74			hlic2: interrupt-controller {
75				#interrupt-cells = < 0x01 >;
76				interrupt-controller;
77				compatible = "riscv,cpu-intc";
78			};
79		};
80
81		cpu@3 {
82			device_type = "cpu";
83			reg = < 0x03 >;
84			status = "okay";
85			compatible = "riscv";
86
87			hlic3: interrupt-controller {
88				#interrupt-cells = < 0x01 >;
89				interrupt-controller;
90				compatible = "riscv,cpu-intc";
91			};
92		};
93
94		cpu@4 {
95			device_type = "cpu";
96			reg = < 0x04 >;
97			status = "okay";
98			compatible = "riscv";
99
100			hlic4: interrupt-controller {
101				#interrupt-cells = < 0x01 >;
102				interrupt-controller;
103				compatible = "riscv,cpu-intc";
104			};
105		};
106
107		cpu@5 {
108			device_type = "cpu";
109			reg = < 0x05 >;
110			status = "okay";
111			compatible = "riscv";
112
113			hlic5: interrupt-controller {
114				#interrupt-cells = < 0x01 >;
115				interrupt-controller;
116				compatible = "riscv,cpu-intc";
117			};
118		};
119
120		cpu@6 {
121			device_type = "cpu";
122			reg = < 0x06 >;
123			status = "okay";
124			compatible = "riscv";
125
126			hlic6: interrupt-controller {
127				#interrupt-cells = < 0x01 >;
128				interrupt-controller;
129				compatible = "riscv,cpu-intc";
130			};
131		};
132
133		cpu@7 {
134			device_type = "cpu";
135			reg = < 0x07 >;
136			status = "okay";
137			compatible = "riscv";
138
139			hlic7: interrupt-controller {
140				#interrupt-cells = < 0x01 >;
141				interrupt-controller;
142				compatible = "riscv,cpu-intc";
143			};
144		};
145	};
146
147	ram0: memory@80000000 {
148		device_type = "memory";
149		reg = < 0x80000000 0x10000000 >;
150	};
151
152	soc {
153		#address-cells = < 0x01 >;
154		#size-cells = < 0x01 >;
155		compatible = "simple-bus";
156		ranges;
157
158		plic: interrupt-controller@c000000 {
159			riscv,max-priority = <7>;
160			riscv,ndev = < 0x35 >;
161			reg = <0x0c000000 0x00002000
162			       0x0c002000 0x001fe000
163			       0x0c200000 0x03e00000>;
164			reg-names = "prio", "irq_en", "reg";
165			interrupts-extended = <
166				&hlic0 0x0b &hlic0 0x09
167				&hlic1 0x0b &hlic1 0x09
168				&hlic2 0x0b &hlic2 0x09
169				&hlic3 0x0b &hlic3 0x09
170				&hlic4 0x0b &hlic4 0x09
171				&hlic5 0x0b &hlic5 0x09
172				&hlic6 0x0b &hlic6 0x09
173				&hlic7 0x0b &hlic7 0x09
174			>;
175			interrupt-controller;
176			compatible = "sifive,plic-1.0.0";
177			#interrupt-cells = < 0x02 >;
178			#address-cells = < 0x00 >;
179		};
180
181		clint@2000000 {
182			interrupts-extended = <
183				&hlic0 0x03 &hlic0 0x07
184				&hlic1 0x03 &hlic1 0x07
185				&hlic2 0x03 &hlic2 0x07
186				&hlic3 0x03 &hlic3 0x07
187				&hlic4 0x03 &hlic4 0x07
188				&hlic5 0x03 &hlic5 0x07
189				&hlic6 0x03 &hlic6 0x07
190				&hlic7 0x03 &hlic7 0x07
191			>;
192			reg = < 0x2000000 0x10000 >;
193			compatible = "riscv,clint0";
194			#interrupt-cells = <1>;
195			interrupt-controller;
196		};
197	};
198};
199