1/*
2 * Copyright 2018 Foundries.io Ltd
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <dt-bindings/interrupt-controller/openisa-intmux.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/i2c/i2c.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	chosen {
15		zephyr,entropy = &trng;
16		zephyr,flash-controller = &ftfe;
17	};
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22		cpu@0 {
23			device_type = "cpu";
24			compatible = "riscv";
25			reg = <0>;
26		};
27
28		cpu@1 {
29			device_type = "cpu";
30			compatible = "riscv";
31			reg = <1>;
32		};
33	};
34
35	m4_dtcm: memory@20000000 {
36		compatible = "mmio-sram";
37		reg = <0x20000000 0x30000>;
38	};
39
40	m0_tcm: memory@9000000 {
41		compatible = "mmio-sram";
42		reg = <0x09000000 0x20000>;
43	};
44
45	soc {
46		#address-cells = <1>;
47		#size-cells = <1>;
48		compatible = "simple-bus";
49		ranges;
50
51		pcc0: clock-controller@4002b000 {
52			compatible = "openisa,rv32m1-pcc";
53			reg = <0x4002b000 0x200>;
54			label = "PCC0";
55			#clock-cells = <1>;
56		};
57
58		pcc1: clock-controller@41027000 {
59			compatible = "openisa,rv32m1-pcc";
60			reg = <0x41027000 0x200>;
61			label = "PCC1";
62			#clock-cells = <1>;
63		};
64
65		event0: interrupt-controller@e0041000 {
66			compatible = "openisa,rv32m1-event-unit";
67			#interrupt-cells = <1>;
68			interrupt-controller;
69			reg = <0xe0041000 0x88>;
70		};
71
72		event1: interrupt-controller@4101f000 {
73			compatible = "openisa,rv32m1-event-unit";
74			#interrupt-cells = <1>;
75			interrupt-controller;
76			reg = <0x4101f000 0x88>;
77		};
78
79		intmux0: intmux@4004f000 {
80			compatible = "openisa,rv32m1-intmux";
81			reg = <0x4004f000 0x200>;
82			clocks = <&pcc0 0x13c>;
83			label = "INTMUX0";
84			status = "disabled";
85			#address-cells = <1>;
86			#size-cells = <1>;
87
88			ranges = <0x0 0x4004f000 0x200>;
89
90			intmux0_ch0: interrupt-controller@0 {
91				compatible = "openisa,rv32m1-intmux-ch";
92				#interrupt-cells = <1>;
93				interrupt-controller;
94				interrupts = <INTMUX_CH0_IRQ>;
95				reg = <0x0 0x40>;
96				label = "INTMUX0_CH0";
97				status = "disabled";
98			};
99
100			intmux0_ch1: interrupt-controller@40 {
101				compatible = "openisa,rv32m1-intmux-ch";
102				#interrupt-cells = <1>;
103				interrupt-controller;
104				interrupts = <INTMUX_CH1_IRQ>;
105				reg = <0x40 0x40>;
106				label = "INTMUX0_CH1";
107				status = "disabled";
108			};
109
110			intmux0_ch2: interrupt-controller@80 {
111				compatible = "openisa,rv32m1-intmux-ch";
112				#interrupt-cells = <1>;
113				interrupt-controller;
114				interrupts = <INTMUX_CH2_IRQ>;
115				reg = <0x80 0x40>;
116				label = "INTMUX0_CH2";
117				status = "disabled";
118			};
119
120			intmux0_ch3: interrupt-controller@c0 {
121				compatible = "openisa,rv32m1-intmux-ch";
122				#interrupt-cells = <1>;
123				interrupt-controller;
124				interrupts = <INTMUX_CH3_IRQ>;
125				reg = <0xc0 0x40>;
126				label = "INTMUX0_CH3";
127				status = "disabled";
128			};
129
130			intmux0_ch4: interrupt-controller@100 {
131				compatible = "openisa,rv32m1-intmux-ch";
132				#interrupt-cells = <1>;
133				interrupt-controller;
134				interrupts = <INTMUX_CH4_IRQ>;
135				reg = <0x100 0x40>;
136				label = "INTMUX0_CH4";
137				status = "disabled";
138			};
139
140			intmux0_ch5: interrupt-controller@140 {
141				compatible = "openisa,rv32m1-intmux-ch";
142				#interrupt-cells = <1>;
143				interrupt-controller;
144				interrupts = <INTMUX_CH5_IRQ>;
145				reg = <0x140 0x40>;
146				label = "INTMUX0_CH5";
147				status = "disabled";
148			};
149
150			intmux0_ch6: interrupt-controller@180 {
151				compatible = "openisa,rv32m1-intmux-ch";
152				#interrupt-cells = <1>;
153				interrupt-controller;
154				interrupts = <INTMUX_CH6_IRQ>;
155				reg = <0x180 0x40>;
156				label = "INTMUX0_CH6";
157				status = "disabled";
158			};
159
160			intmux0_ch7: interrupt-controller@1c0 {
161				compatible = "openisa,rv32m1-intmux-ch";
162				#interrupt-cells = <1>;
163				interrupt-controller;
164				interrupts = <INTMUX_CH7_IRQ>;
165				reg = <0x1c0 0x40>;
166				label = "INTMUX0_CH7";
167				status = "disabled";
168			};
169		};
170
171		intmux1: intmux@41022000 {
172			compatible = "openisa,rv32m1-intmux";
173			reg = <0x41022000 0x20>;
174			clocks = <&pcc1 0x88>;
175			label = "INTMUX1";
176			status = "disabled";
177			#address-cells = <1>;
178			#size-cells = <1>;
179
180			ranges = <0x0 0x41022000 0x200>;
181
182			intmux1_ch0: interrupt-controller@0 {
183				compatible = "openisa,rv32m1-intmux-ch";
184				#interrupt-cells = <1>;
185				interrupt-controller;
186				interrupts = <INTMUX_CH0_IRQ>;
187				reg = <0x0 0x40>;
188				label = "INTMUX1_CH0";
189				status = "disabled";
190			};
191
192			intmux1_ch1: interrupt-controller@40 {
193				compatible = "openisa,rv32m1-intmux-ch";
194				#interrupt-cells = <1>;
195				interrupt-controller;
196				interrupts = <INTMUX_CH1_IRQ>;
197				reg = <0x40 0x40>;
198				label = "INTMUX1_CH1";
199				status = "disabled";
200			};
201
202			intmux1_ch2: interrupt-controller@80 {
203				compatible = "openisa,rv32m1-intmux-ch";
204				#interrupt-cells = <1>;
205				interrupt-controller;
206				interrupts = <INTMUX_CH2_IRQ>;
207				reg = <0x80 0x40>;
208				label = "INTMUX1_CH2";
209				status = "disabled";
210			};
211
212			intmux1_ch3: interrupt-controller@c0 {
213				compatible = "openisa,rv32m1-intmux-ch";
214				#interrupt-cells = <1>;
215				interrupt-controller;
216				interrupts = <INTMUX_CH3_IRQ>;
217				reg = <0xc0 0x40>;
218				label = "INTMUX1_CH3";
219				status = "disabled";
220			};
221
222			intmux1_ch4: interrupt-controller@100 {
223				compatible = "openisa,rv32m1-intmux-ch";
224				#interrupt-cells = <1>;
225				interrupt-controller;
226				interrupts = <INTMUX_CH4_IRQ>;
227				reg = <0x100 0x40>;
228				label = "INTMUX1_CH4";
229				status = "disabled";
230			};
231
232			intmux1_ch5: interrupt-controller@140 {
233				compatible = "openisa,rv32m1-intmux-ch";
234				#interrupt-cells = <1>;
235				interrupt-controller;
236				interrupts = <INTMUX_CH5_IRQ>;
237				reg = <0x140 0x40>;
238				label = "INTMUX1_CH5";
239				status = "disabled";
240			};
241
242			intmux1_ch6: interrupt-controller@180 {
243				compatible = "openisa,rv32m1-intmux-ch";
244				#interrupt-cells = <1>;
245				interrupt-controller;
246				interrupts = <INTMUX_CH6_IRQ>;
247				reg = <0x180 0x40>;
248				label = "INTMUX1_CH6";
249				status = "disabled";
250			};
251
252			intmux1_ch7: interrupt-controller@1c0 {
253				compatible = "openisa,rv32m1-intmux-ch";
254				#interrupt-cells = <1>;
255				interrupt-controller;
256				interrupts = <INTMUX_CH7_IRQ>;
257				reg = <0x1c0 0x40>;
258				label = "INTMUX1_CH7";
259				status = "disabled";
260			};
261		};
262
263		lptmr0: timer@40032000 {
264			compatible = "openisa,rv32m1-lptmr";
265			reg = <0x40032000 0x10>;
266			label = "LPTMR_0";
267		};
268
269		lptmr1: timer@40033000 {
270			compatible = "openisa,rv32m1-lptmr";
271			reg = <0x40033000 0x10>;
272			label = "LPTMR_1";
273		};
274
275		lptmr2: timer@4102b000 {
276			compatible = "openisa,rv32m1-lptmr";
277			reg = <0x4102b000 0x10>;
278			label = "LPTMR_2";
279		};
280
281		porta: pinmux@40046000 {
282			compatible = "openisa,rv32m1-pinmux";
283			reg = <0x40046000 0xd0>;
284			clocks = <&pcc0 0x118>;
285		};
286
287		portb: pinmux@40047000 {
288			compatible = "openisa,rv32m1-pinmux";
289			reg = <0x40047000 0xd0>;
290			clocks = <&pcc0 0x11c>;
291		};
292
293		portc: pinmux@40048000 {
294			compatible = "openisa,rv32m1-pinmux";
295			reg = <0x40048000 0xd0>;
296			clocks = <&pcc0 0x120>;
297		};
298
299		portd: pinmux@40049000 {
300			compatible = "openisa,rv32m1-pinmux";
301			reg = <0x40049000 0xd0>;
302			clocks = <&pcc0 0x124>;
303		};
304
305		porte: pinmux@41037000 {
306			compatible = "openisa,rv32m1-pinmux";
307			reg = <0x41037000 0xd0>;
308			clocks = <&pcc1 0xdc>;
309		};
310
311		gpioa: gpio@48020000 {
312			compatible = "openisa,rv32m1-gpio";
313			reg = <0x48020000 0x14>;
314			label = "GPIO_0";
315			gpio-controller;
316			#gpio-cells = <2>;
317			openisa,rv32m1-port = <&porta>;
318		};
319
320		gpiob: gpio@48020040 {
321			compatible = "openisa,rv32m1-gpio";
322			reg = <0x48020040 0x14>;
323			label = "GPIO_1";
324			gpio-controller;
325			#gpio-cells = <2>;
326			openisa,rv32m1-port = <&portb>;
327		};
328
329		gpioc: gpio@48020080 {
330			compatible = "openisa,rv32m1-gpio";
331			reg = <0x48020080 0x14>;
332			label = "GPIO_2";
333			gpio-controller;
334			#gpio-cells = <2>;
335			openisa,rv32m1-port = <&portc>;
336		};
337
338		gpiod: gpio@480200c0 {
339			compatible = "openisa,rv32m1-gpio";
340			reg = <0x480200c0 0x14>;
341			label = "GPIO_3";
342			gpio-controller;
343			#gpio-cells = <2>;
344			openisa,rv32m1-port = <&portd>;
345		};
346
347		gpioe: gpio@4100f000 {
348			compatible = "openisa,rv32m1-gpio";
349			reg = <0x4100f000 0x14>;
350			label = "GPIO_4";
351			gpio-controller;
352			#gpio-cells = <2>;
353			clocks = <&pcc1 0x3c>;
354			openisa,rv32m1-port = <&porte>;
355		};
356
357		lpuart0: lpuart@40042000 {
358			compatible = "openisa,rv32m1-lpuart";
359			reg = <0x40042000 0x2c>;
360			clocks = <&pcc0 0x108>;
361			label = "UART_0";
362			status = "disabled";
363		};
364
365		lpuart1: lpuart@40043000 {
366			compatible = "openisa,rv32m1-lpuart";
367			reg = <0x40043000 0x2c>;
368			clocks = <&pcc0 0x10c>;
369			label = "UART_1";
370			status = "disabled";
371		};
372
373		lpuart2: lpuart@40044000 {
374			compatible = "openisa,rv32m1-lpuart";
375			reg = <0x40044000 0x2c>;
376			clocks = <&pcc0 0x110>;
377			label = "UART_2";
378			status = "disabled";
379		};
380
381		lpuart3: lpuart@41036000 {
382			compatible = "openisa,rv32m1-lpuart";
383			reg = <0x41036000 0x2c>;
384			clocks = <&pcc0 0xd8>;
385			label = "UART_3";
386			status = "disabled";
387		};
388
389		lpi2c0: lpi2c@4003a000 {
390			compatible = "openisa,rv32m1-lpi2c";
391			reg = <0x4003a000 0x170>;
392			clocks = <&pcc0 0xe8>;
393			label = "I2C_0";
394			clock-frequency = <I2C_BITRATE_STANDARD>;
395			#address-cells = <1>;
396			#size-cells = <0>;
397			status = "disabled";
398		};
399
400		lpi2c1: lpi2c@4003b000 {
401			compatible = "openisa,rv32m1-lpi2c";
402			reg = <0x4003b000 0x170>;
403			clocks = <&pcc0 0xec>;
404			label = "I2C_1";
405			clock-frequency = <I2C_BITRATE_STANDARD>;
406			#address-cells = <1>;
407			#size-cells = <0>;
408			status = "disabled";
409		};
410
411		lpi2c2: lpi2c@4003c000 {
412			compatible = "openisa,rv32m1-lpi2c";
413			reg = <0x4003c000 0x170>;
414			clocks = <&pcc0 0xf0>;
415			label = "I2C_2";
416			clock-frequency = <I2C_BITRATE_STANDARD>;
417			#address-cells = <1>;
418			#size-cells = <0>;
419			status = "disabled";
420		};
421
422		lpi2c3: lpi2c@4102e000 {
423			compatible = "openisa,rv32m1-lpi2c";
424			reg = <0x4102e000 0x170>;
425			clocks = <&pcc1 0xb8>;
426			label = "I2C_3";
427			clock-frequency = <I2C_BITRATE_STANDARD>;
428			#address-cells = <1>;
429			#size-cells = <0>;
430			status = "disabled";
431		};
432
433		lpspi0: spi@4003f000 {
434			compatible = "openisa,rv32m1-lpspi";
435			reg = <0x4003f000 0x78>;
436			label = "SPI_0";
437			status = "disabled";
438			clocks = <&pcc0 0xfc>;
439			#address-cells = <1>;
440			#size-cells = <0>;
441		};
442
443		lpspi1: spi@40040000 {
444			compatible = "openisa,rv32m1-lpspi";
445			reg = <0x40040000 0x78>;
446			label = "SPI_1";
447			status = "disabled";
448			clocks = <&pcc0 0x100>;
449			#address-cells = <1>;
450			#size-cells = <0>;
451		};
452
453		lpspi2: spi@40041000 {
454			compatible = "openisa,rv32m1-lpspi";
455			reg = <0x40041000 0x78>;
456			label = "SPI_2";
457			status = "disabled";
458			clocks = <&pcc0 0x104>;
459			#address-cells = <1>;
460			#size-cells = <0>;
461		};
462
463		lpspi3: spi@41035000 {
464			compatible = "openisa,rv32m1-lpspi";
465			reg = <0x41035000 0x78>;
466			label = "SPI_3";
467			status = "disabled";
468			clocks = <&pcc1 0xd4>;
469			#address-cells = <1>;
470			#size-cells = <0>;
471		};
472
473		generic_fsk: generic_fsk@41033000 {
474			compatible = "openisa,rv32m1-genfsk";
475			reg = <0x41033000 0x90>;
476			#address-cells = <1>;
477			#size-cells = <0>;
478		};
479
480		tpm0: pwm@40035000 {
481			compatible = "openisa,rv32m1-tpm";
482			reg = <0x40035000 0x88>;
483			clocks = <&pcc0 0xd4>;
484			label = "PWM_0";
485			status = "disabled";
486			#pwm-cells = <3>;
487		};
488
489		tpm1: pwm@40036000 {
490			compatible = "openisa,rv32m1-tpm";
491			reg = <0x40036000 0x88>;
492			clocks = <&pcc0 0xd8>;
493			label = "PWM_1";
494			status = "disabled";
495			#pwm-cells = <3>;
496		};
497
498		tpm2: pwm@40037000 {
499			compatible = "openisa,rv32m1-tpm";
500			reg = <0x40037000 0x88>;
501			clocks = <&pcc0 0xdc>;
502			label = "PWM_2";
503			status = "disabled";
504			#pwm-cells = <3>;
505		};
506
507		trng: random@41029000{
508			compatible = "openisa,rv32m1-trng";
509			reg = <0x41029000 0x1000>;
510			status = "okay";
511			interrupts = <13 0>;
512			label = "TRNG";
513		};
514
515		tpm3: pwm@4102d000 {
516			compatible = "openisa,rv32m1-tpm";
517			reg = <0x4102d000 0x88>;
518			clocks = <&pcc1 0xb4>;
519			label = "PWM_3";
520			status = "disabled";
521			#pwm-cells = <3>;
522		};
523
524		ftfe: flash-controller@40023000 {
525			compatible = "openisa,rv32m1-ftfe";
526			label = "FLASH_CTRL";
527			reg = <0x40023000 0x18>;
528
529			#address-cells = <1>;
530			#size-cells = <1>;
531
532			m4_flash: flash@0 {
533				compatible = "soc-nv-flash";
534				label = "M4_FLASH";
535				reg = <0 0x100000>;
536				erase-block-size = <4096>;
537				write-block-size = <8>;
538			};
539
540			m0_flash: flash@1000000 {
541				compatible = "soc-nv-flash";
542				label = "M0_FLASH";
543				reg = <0x01000000 0x40000>;
544				erase-block-size = <4096>;
545				write-block-size = <8>;
546			};
547		};
548	};
549};
550