1# Copyright (c) 2019 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4menuconfig DW_ICTL
5	bool "Designware Interrupt Controller"
6	depends on MULTI_LEVEL_INTERRUPTS
7	help
8	  Designware Interrupt Controller can be used as a 2nd level interrupt
9	  controller which combines several sources of interrupt into one line
10	  that is then routed to the 1st level interrupt controller.
11
12if DW_ICTL
13
14config DW_ICTL_NAME
15	string "Name for Designware Interrupt Controller"
16	default "DW_ICTL"
17	help
18	  Give a name for the instance of Designware Interrupt Controller
19
20config DW_ICTL_OFFSET
21	int "Parent interrupt number to which DW_ICTL maps"
22	default 0
23	help
24	  Parent interrupt number to which DW_ICTL maps
25
26config DW_ISR_TBL_OFFSET
27	int "Offset in the SW ISR Table"
28	default 0
29	help
30	  This indicates the offset in the SW_ISR_TABLE beginning from where
31	  the ISRs for Designware Interrupt Controller are assigned.
32
33config DW_ICTL_INIT_PRIORITY
34	int "Init priority for DW interrupt controller"
35	default 48
36	help
37	  DesignWare Interrupt Controller initialization priority.
38
39endif # DW_ICTL
40