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/Zephyr-Core-3.5.0/boards/arm/qomu/
Dqomu.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
19 zephyr,shell-uart = &uart1;
20 zephyr,uart-pipe = &uart1;
31 compatible = "gpio-leds";
49 compatible = "gpio-keys";
65 input-enable;
69 output-enable;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dquicklogic,eos-s3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
18 input-enable;
22 output-enable;
26 compatible: "quicklogic,eos-s3-pinctrl"
34 child-binding:
40 - name: pincfg-node.yaml
41 property-allowlist:
42 - input-enable
43 - output-enable
[all …]
Dnuvoton,npcx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
6 pin function selection and pin properties. For example, you can use these
10 - bias-pull-down: Enable pull-down resistor.
11 - bias-pull-up: Enable pull-up resistor.
12 - drive-open-drain: Output driver is open-drain.
15 - pinmux-locked: Lock pinmux configuration for peripheral device
16 - pinmux-gpio: Inverse pinmux back to gpio
17 - psl-in-mode: Select the assertion detection mode of PSL input
18 - psl-in-pol: Select the assertion detection polarity of PSL input
23 #include <nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi>
[all …]
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 RT600/RT500 pin control node. This node defines pin configurations in pin
17 slew-rate = "normal";
18 drive-strength = "normal";
24 IOCON_FUNC=<pin mux selection>,
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
37 bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
[all …]
Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
[all …]
Dinfineon,cat1-pinctrl.yaml4 # SPDX-License-Identifier: Apache-2.0
9 This is a singleton node responsible for controlling the pin function selection
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
[all …]
Dnxp,s32ze-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
40 'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41 'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42 output buffer use 'output-enable'.
44 To link the pin configurations with UART0 device, use pinctrl-N property in the
45 device node, where 'N' is the zero-based state index (0 is the default state).
[all …]
/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
21 /* gpio port control register (byte mapping to pin) */
23 /* function 3 general control register */
27 /* function 3 external control register */
31 /* function 4 general control register */
35 /* Input voltage selection */
37 /* Input voltage selection mask */
43 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
47 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
[all …]
/Zephyr-Core-3.5.0/drivers/ieee802154/
Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
110 /* Disable Smart TX Power control */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
123 /* Automatic Acknowledgement Pending bit control */
126 /* System Time Counter (40-bit) */
[all …]
/Zephyr-Core-3.5.0/soc/arm/st_stm32/stm32f1/
DKconfig.soc3 # Copyright (c) 2016 Open-RnD Sp. z o.o.
5 # SPDX-License-Identifier: Apache-2.0
8 prompt "STM32F1x MCU Selection"
50 * XL-density devices Value line devices
57 connectivity and real-time performances are required such as
58 industrial control, control panels for security applications, UPS or
/Zephyr-Core-3.5.0/soc/arm/nxp_kinetis/ke1xf/
DKconfig.soc4 # SPDX-License-Identifier: Apache-2.0
7 prompt "Kinetis KE1xF MCU Selection"
78 number selection choice defines the default value for this
86 source. The application can take over control of the
/Zephyr-Core-3.5.0/drivers/led/
Dis31fl3733.c2 * Copyright 2022-2023 Daniel DeGrasse <daniel@degrasse.com>
4 * SPDX-License-Identifier: Apache-2.0
19 #define CMD_SEL_REG 0xFD /* Command/page selection reg */
24 #define CMD_LOCK_REG 0xFE /* Command selection lock reg */
36 #define GLOBAL_CURRENT_CTRL_REG 0x1 /* global current control register */
70 const struct is31fl3733_config *config = dev->config; in is31fl3733_select_page()
71 struct is31fl3733_data *data = dev->data; in is31fl3733_select_page()
74 if (data->selected_page == page) { in is31fl3733_select_page()
79 /* Unlock page selection register */ in is31fl3733_select_page()
80 ret = i2c_reg_write_byte_dt(&config->bus, CMD_LOCK_REG, CMD_LOCK_UNLOCK); in is31fl3733_select_page()
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_ps2.h4 * SPDX-License-Identifier: Apache-2.0
15 * Writes -> Transmit buffer
16 * Read <- Receive buffer
20 /* PS2 Control register */
32 /* Protocol parity selection */
41 /* Protocol stop bit selection */
54 /* RX Data Ready(Read-Only) */
66 /* Transmitter is Idle(Read-Only) */
72 /* RX is Busy(Read-Only) */
/Zephyr-Core-3.5.0/dts/bindings/rtc/
Dnxp,pcf8523.yaml1 # Copyright (c) 2019-2023 Henrik Brix Andersen <henrik@brixandersen.dk>
2 # SPDX-License-Identifier: Apache-2.0
9 - name: rtc-device.yaml
10 - name: i2c-device.yaml
11 - name: pm.yaml
12 property-allowlist:
13 - wakeup-source
16 quartz-load-femtofarads:
19 - 7000
20 - 12500
[all …]
/Zephyr-Core-3.5.0/subsys/mgmt/mcumgr/transport/
DKconfig.udp2 # Copyright Nordic Semiconductor ASA 2020-2022. All rights reserved.
3 # SPDX-License-Identifier: Apache-2.0
6 # subsystem and provides Kconfig options to control aspects of
63 MCUMGR_TRANSPORT_UDP_MTU <= MCUMGR_TRANSPORT_NETBUF_SIZE + SMP msg overhead - address size
64 where address size is determined by IPv4/IPv6 selection.
/Zephyr-Core-3.5.0/samples/boards/nrf/dynamic_pinctrl/
DREADME.rst3 Dynamic Pin Control (nRF)
6 The Dynamic Pin Control (nRF) sample demonstrates how to change ``uart0`` at
8 push-button.
22 The Dynamic Pin Control (nRF) sample allows you to select the appropriate routing.
38 .. figure:: images/nrf52840dk-dynamic-pinctrl.png
54 .. zephyr-app-commands::
55 :zephyr-app: samples/boards/nrf/dynamic_pinctrl
69 1. Connect a USB-to-UART adapter to both sets of pins. If the board routes the
76 .. figure:: images/terminals-empty.png
83 .. figure:: images/terminals-default.png
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dstm32l1_clock.h4 * SPDX-License-Identifier: Apache-2.0
18 /* RM0038.pdf, §6.3.14 Control/status register (RCC_CSR) */
39 * - reg (1/2/3) [ 0 : 7 ]
40 * - shift (0..31) [ 8 : 12 ]
41 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ]
42 * - val (0..7) [ 16 : 18 ]
60 /** Dummy: Add a specificier when no selection is possible */
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
18 /* Pinmux control group */
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
41 * Pin pull-up/down config [ 4 : 5 ]
42 * Pin voltage selection [ 8 ]
44 * Pin push-pull/open-drain [ 16 ]
56 /* Pin tri-state mode. */
59 /* Pin pull-up or pull-down */
[all …]
/Zephyr-Core-3.5.0/drivers/serial/
Duart_lpc11u6x.h4 * SPDX-License-Identifier: Apache-2.0
105 volatile uint32_t fcr; /* FIFO Control */
107 volatile uint32_t lcr; /* Line Control */
108 volatile uint32_t mcr; /* Modem Control */
112 volatile uint32_t acr; /* Auto-baud Control */
113 volatile uint32_t icr; /* IrDA Control */
121 volatile uint32_t rs485_ctrl; /* RS-485 control */
122 volatile uint32_t rs485_addr_match; /* RS-485 address match */
123 volatile uint32_t rs485_dly; /* RS-485 delay direction control
126 volatile uint32_t sync_ctrl; /* Synchronous mode control */
[all …]
/Zephyr-Core-3.5.0/boards/arm/cy8ckit_062_wifi_bt/doc/
Dindex.rst3 INFINEON PSoC6 WiFi-BT Pioneer Kit
9 The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware
13 The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a
14 dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application
15 processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations,
17 56 programmable digital blocks, Full-Speed USB, a serial memory interface,
18 a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing
21 The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields.
23 The Cortex-M0+ is a primary core on the board's SoC. It starts first and
32 3. KitProg2 USB Type-C connector (J10)
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_gpio.h4 * SPDX-License-Identifier: Apache-2.0
22 /* GPIO Control register field definitions. */
24 /* bits[1:0] internal pull up/down selection */
54 /* bit[8] output buffer type: push-pull or open-drain */
69 * Set bit[10]=1 if you wish to control pin output using the parallel
116 * Each GPIO pin implements a second control register.
117 * GPIO Control 2 register selects pin drive strength and slew rate.
/Zephyr-Core-3.5.0/drivers/ethernet/
Deth_smsc91x_priv.h3 * SPDX-License-Identifier: Apache-2.0
17 /* Bank 0, Offset 0x0: Transmit Control Register */
26 /* Bank 0, Offset 0x4: Receive Control Register */
45 /* bank 0, offset 0xa: receive/phy control register */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
49 #define RPCR_SPEED 0x2000 /* Manual speed selection */
54 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
75 /* Bank 1, Offset 0xc: Control Register */
144 /* Control Byte */
156 /* Length of status word + byte count + control bytes for packets */
/Zephyr-Core-3.5.0/dts/bindings/pwm/
Despressif,esp32-ledc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 The LEDC controller is primarily designed to control the intensity of LEDs, although it can be
14 pinctrl-0 = <&ledc0_default>;
15 pinctrl-names = "default";
18 The 'ledc0_default' node state is defined in <board>-pinctrl.dtsi.
25 output-enable;
29 If another GPIO mapping is desired, check if <board>-pinctrl.dtsi already have it defined,
33 https://github.com/zephyrproject-rtos/hal_espressif/tree/zephyr/include/dt-bindings/pinctrl
46 output-enable;
55 pinctrl-0 = <&ledc0_custom>;
[all …]
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/same70/
DKconfig.soc4 # SPDX-License-Identifier: Apache-2.0
7 prompt "Atmel SAME70 MCU Selection"
85 needs to stabilize after power-up.
100 stabilize after power-up.
164 switch the pin to general IO mode giving control of the pin to the GPIO
/Zephyr-Core-3.5.0/soc/arm/atmel_sam/samv71/
DKconfig.soc5 # SPDX-License-Identifier: Apache-2.0
8 prompt "Atmel SAMV71 MCU Selection"
86 needs to stabilize after power-up.
101 stabilize after power-up.
165 switch the pin to general IO mode giving control of the pin to the GPIO

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