1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  NXP S32 pinctrl node for S32K3 SoCs.
6
7  The NXP S32 pin controller is a singleton node responsible for controlling
8  the pin function selection and pin properties. This node, labeled 'pinctrl' in
9  the SoC's devicetree, will define pin configurations in pin groups. Each group
10  within the pin configuration defines the pin configuration for a peripheral,
11  and each numbered subgroup in the pin group defines all the pins for that
12  peripheral with the same configuration properties. The 'pinmux' property in
13  a group selects the pins to be configured, and the remaining properties set
14  configuration values for those pins.
15
16  For example, to configure the pinmux for UART0, modify the 'pinctrl' from your
17  board or application devicetree overlay as follows:
18
19    /* Include the SoC package header containing the predefined pins definitions */
20    #include <nxp/s32/S32K344-257BGA-pinctrl.h>
21
22    &pinctrl {
23      uart0_default: uart0_default {
24        group1 {
25          pinmux = <PTA3_LPUART0_TX_O>;
26          output-enable;
27        };
28        group2 {
29          pinmux = <PTA28_LPUART0_RX>;
30          input-enable;
31        };
32      };
33    };
34
35  The 'uart0_default' node contains the pin configurations for a particular state
36  of a device. The 'default' state is the active state. Other states for the same
37  device can be specified in separate child nodes of 'pinctrl'.
38
39  In addition to 'pinmux' property, each group can contain other properties such as
40  'bias-pull-up' or 'slew-rate' that will be applied to all the pins defined in
41  'pinmux' array. To enable the input buffer use 'input-enable' and to enable the
42  output buffer use 'output-enable'.
43
44  To link the pin configurations with UART0 device, use pinctrl-N property in the
45  device node, where 'N' is the zero-based state index (0 is the default state).
46  Following previous example:
47
48    &uart0 {
49      pinctrl-0 = <&uart0_default>;
50      pinctrl-names = "default";
51      status = "okay";
52    };
53
54  If only the required properties are supplied, the pin configuration register
55  will be assigned the following values:
56    - input and output buffers disabled
57    - internal pull not enabled
58    - slew rate "fastest"
59    - invert disabled
60    - drive strength disabled.
61
62  Additionally, following settings are currently not supported and default to
63  the values indicated below:
64    - Safe Mode Control (disabled)
65    - Pad Keeping (disabled)
66    - Input Filter (disabled).
67
68compatible: "nxp,s32k3-pinctrl"
69
70include: base.yaml
71
72child-binding:
73  description: NXP S32 pin controller pin group.
74  child-binding:
75    description: NXP S32 pin controller pin configuration node.
76
77    include:
78      - name: pincfg-node.yaml
79        property-allowlist:
80          - bias-disable
81          - bias-pull-down
82          - bias-pull-up
83          - input-enable
84          - output-enable
85
86    properties:
87      pinmux:
88        required: true
89        type: array
90        description: |
91          An array of pins sharing the same group properties. The pins must be
92          defined using the S32_PINMUX macros that encodes all the pin muxing
93          information in a 32-bit value.
94
95      slew-rate:
96        type: string
97        enum:
98          - "fastest"
99          - "slowest"
100        default: "fastest"
101        description: |
102          Slew rate control. Can be either slowest or fastest setting.
103          See the SoC reference manual for applicability of this setting.
104
105      nxp,invert:
106        type: boolean
107        description: |
108          Invert the signal selected by Source Signal Selection (SSS) before
109          transmitting it to the associated destination (chip pin or module port).
110
111      nxp,drive-strength:
112        type: boolean
113        description: |
114          Drive strength enable.
115          See the SoC reference manual for applicability of this setting.
116