1# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 6 Espressif's LEDC controller Node 7 8 The LEDC controller is primarily designed to control the intensity of LEDs, although it can be 9 used to generate PWM signals for other purposes as well. 10 11 The mapping between the channel and GPIO is done through pinctrl 12 13 &ledc0 { 14 pinctrl-0 = <&ledc0_default>; 15 pinctrl-names = "default"; 16 } 17 18 The 'ledc0_default' node state is defined in <board>-pinctrl.dtsi. 19 20 ledc0_default: ledc0_default { 21 group1 { 22 pinmux = <LEDC_CH0_GPIO0>, 23 <LEDC_CH1_GPIO2>, 24 <LEDC_CH2_GPIO4>; 25 output-enable; 26 }; 27 }; 28 29 If another GPIO mapping is desired, check if <board>-pinctrl.dtsi already have it defined, 30 otherwise, define the required mapping at your own application folder into a custom 31 <board>.overlay file. 32 The 'pinmux' property uses a macro defined in 33 https://github.com/zephyrproject-rtos/hal_espressif/tree/zephyr/include/dt-bindings/pinctrl 34 Before including a new node, check if the desired mapping is available according to the SoC. 35 36 As an example, the 'ledc0_custom' state below illustrates an alternate mapping using another set 37 of channels and pins in a custom overlay file. 38 39 &pinctrl { 40 41 ledc0_custom: ledc0_custom { 42 group1 { 43 pinmux = <LEDC_CH0_GPIO0>, 44 <LEDC_CH9_GPIO2>, 45 <LEDC_CH10_GPIO4>; 46 output-enable; 47 }; 48 }; 49 50 }; 51 52 Use the child bindings to configure the desired channel: 53 54 &ledc0 { 55 pinctrl-0 = <&ledc0_custom>; 56 pinctrl-names = "default"; 57 status = "okay"; 58 #address-cells = <1>; 59 #size-cells = <0>; 60 channel0@0 { 61 reg = <0x0>; 62 timer = <0>; 63 }; 64 channel9@9 { 65 reg = <0x9>; 66 timer = <0>; 67 }; 68 channel10@a { 69 reg = <0xa>; 70 timer = <1>; 71 }; 72 }; 73 74 Note: The channel's 'reg' property defines the ID of the channel. It must match the channel used 75 in the 'pinmux'. 76 77 78compatible: "espressif,esp32-ledc" 79 80include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml] 81 82properties: 83 "#pwm-cells": 84 const: 3 85 86child-binding: 87 description: Channel configuration. 88 89 properties: 90 reg: 91 type: int 92 required: true 93 enum: 94 - 0 95 - 1 96 - 2 97 - 3 98 - 4 99 - 5 100 - 6 101 - 7 102 - 8 103 - 9 104 - 10 105 - 11 106 - 12 107 - 13 108 - 14 109 - 15 110 111 description: | 112 The ESP32 has 8 low speed channel and 8 high speed channels. 113 The low speed channel are mapped from channel 0 to 7, and the high speed are mapped from 114 channel 8 to 15. 115 116 High speed channels are only available in the ESP32 SoC. ESP32S2 and ESP32S3 have 8 117 available channels, and ESP32C3 has 6. In these SoCs there is no differentiation between 118 low or high speed. 119 120 timer: 121 type: int 122 required: true 123 enum: 124 - 0 125 - 1 126 - 2 127 - 3 128 description: | 129 Timer selection. 130 For maximum flexibility, the high-speed as well as the low-speed channels can be driven from 131 one of four high-speed/low-speed timers. 132 133pwm-cells: 134- channel 135- period 136- flags 137