1# Copyright (c) 2023 Antmicro <www.antmicro.com> 2# SPDX-License-Identifier: Apache-2.0 3 4description: | 5 Quicklogic EOS S3 IO MUX binding covers the 46 IOMUX_PAD_x_CTRL registers 6 that can be used to set the direction and the function of a pad. 7 8 Device pin configuration should be placed in the child nodes of this node. 9 Populate the 'pinmux' field with IO function and pin number. 10 11 For example, setting pins 44 and 45 for use as UART would look like this: 12 13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h> 14 15 &pinctrl { 16 uart0_rx_default: uart0_rx_default { 17 pinmux = <UART_RX_PAD45>; 18 input-enable; 19 }; 20 uart0_tx_default: uart0_tx_default { 21 pinmux = <UART_TX_PAD44>; 22 output-enable; 23 }; 24 }; 25 26compatible: "quicklogic,eos-s3-pinctrl" 27 28include: base.yaml 29 30properties: 31 reg: 32 required: true 33 34child-binding: 35 description: | 36 This binding gives a base representation of the SiFive FE310 pins 37 configuration. 38 39 include: 40 - name: pincfg-node.yaml 41 property-allowlist: 42 - input-enable 43 - output-enable 44 - bias-pull-up 45 - bias-pull-down 46 - bias-high-impedance 47 - input-schmitt-enable 48 - drive-strength 49 properties: 50 pinmux: 51 required: true 52 type: array 53 description: | 54 Quicklogic EOS S3 pin's configuration (pin, IO function). 55 slew-rate: 56 description: | 57 The default value "slow" matches the power-on reset value. 58 default: "slow" 59 type: string 60 enum: 61 - "slow" 62 - "fast" 63 quicklogic,control-selection: 64 description: | 65 Control selection for IO output. 66 It's either controlled from registers of the A0 always-on domain, 67 fabric-controlled for signaling with FPGA, 68 or other-controller for bidirectional signals. 69 The default value "a0registers" matches the power-on reset value. 70 default: "a0registers" 71 type: string 72 enum: 73 - "a0registers" 74 - "others" 75 - "fabric" 76