Searched full:configuration (Results 1 – 25 of 379) sorted by relevance
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| /trusted-firmware-a-3.7.0/include/drivers/nxp/ddr/ |
| D | immap.h | 30 unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
31 unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
32 unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
33 unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
34 unsigned int sdram_cfg; /* SDRAM Control Configuration */
35 unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
36 unsigned int sdram_mode; /* SDRAM Mode Configuration */
37 unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
39 unsigned int sdram_interval; /* SDRAM Interval Configuration */
47 unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
[all …]
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| /trusted-firmware-a-3.7.0/plat/renesas/common/include/registers/ |
| D | axi_registers.h | 33 /* AXI decompression area configuration A0 */
35 /* AXI decompression area configuration B0 */
37 /* AXI decompression area configuration A1 */
39 /* AXI decompression area configuration B1 */
41 /* AXI decompression area configuration A2 */
43 /* AXI decompression area configuration B2 */
45 /* AXI decompression area configuration A3 */
47 /* AXI decompression area configuration B3 */
49 /* AXI decompression area configuration A4 */
51 /* AXI decompression area configuration B4 */
[all …]
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a70x0_mochabin/board/ |
| D | dram_port.c | 19 * configuration located on non volatile storage
27 * the appropriate board DRAM configuration
51 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
55 { /* electrical configuration */
56 { /* memory electrical configuration */
68 { /* phy electrical configuration */
82 { /* mac electrical configuration */
113 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
117 { /* electrical configuration */
118 { /* memory electrical configuration */
[all …]
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| /trusted-firmware-a-3.7.0/docs/components/fconf/ |
| D | fconf_properties.rst | 8 Dynamic configuration
17 Then a list of subnodes representing a configuration |DTB|, which can be used
23 - Physical loading base address of the configuration.
29 - Maximum size of the configuration.
33 - Image ID of the configuration.
37 - A platform uses this physical address to copy the configuration to
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| D | index.rst | 1 Firmware Configuration Framework
9 The Firmware CONfiguration Framework (|FCONF|) is an abstraction layer for
29 - (|TBBR|) dynamic configuration info: tbbr.dyn_config.disable_auth
49 configuration properties which is usually a device tree file.
56 - HW_CONFIG: properties related to hardware configuration of the SoC
128 - Dynamic configuration information: dyn_cfg.dtb_info.hw_config_id
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a70x0/board/ |
| D | dram_port.c | 17 * configuration located on non volatile storage
25 * the appropriate board DRAM configuration
48 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
52 { /* electrical configuration */
53 { /* memory electrical configuration */
65 { /* phy electrical configuration */
79 { /* mac electrical configuration */
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a70x0_amc/board/ |
| D | dram_port.c | 17 * configuration located on non volatile storage
25 * the appropriate board DRAM configuration
48 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
52 { /* electrical configuration */
53 { /* memory electrical configuration */
65 { /* phy electrical configuration */
79 { /* mac electrical configuration */
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| /trusted-firmware-a-3.7.0/include/drivers/st/ |
| D | stm32mp_ddrctrl_regs.h | 78 uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
79 uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */
104 uint32_t odtcfg; /* 0x240 ODT Configuration */
125 uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
133 uint32_t pccfg; /* 0x400 Port Common Configuration */
136 uint32_t pcfgr_0; /* 0x404 Configuration Read */
137 uint32_t pcfgw_0; /* 0x408 Configuration Write */
140 uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
141 uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
142 uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
[all …]
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| D | stm32mp1_ddr_regs.h | 17 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
24 uint32_t aciocr; /* 0x24 AC I/O Configuration */
25 uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
26 uint32_t dsgcr; /* 0x2C DDR System General Configuration */
27 uint32_t dcr; /* 0x30 DRAM Configuration */
35 uint32_t odtcr; /* 0x50 ODT Configuration */
44 uint32_t dcugcr; /* 0xd0 DCU General Configuration */
74 uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
81 uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
89 uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
[all …]
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| /trusted-firmware-a-3.7.0/plat/intel/soc/common/include/ |
| D | socfpga_handoff.h | 28 /* pinmux configuration - select */
34 /* pinmux configuration - io control */
40 /* pinmux configuration - use fpga switch */
48 /* pinmux configuration - io delay */
54 /* clock configuration */
166 /* misc configuration */
172 /* peripheral configuration - select */
178 /* ddr configuration - select */
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| /trusted-firmware-a-3.7.0/docs/plat/marvell/armada/misc/ |
| D | mvebu-ccu.rst | 4 CCU configuration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The CCU node includes a description of the address decoding configuration.
12 Return the CCU windows configuration and the number of windows of the
19 Array that includes the configuration of the windows. Every window/entry is
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| D | mvebu-iob.rst | 4 IO bridge configuration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The IOB includes a description of the address decoding configuration.
17 Returns the IOB windows configuration and the number of windows
23 Array that includes the configuration of the windows. Every window/entry is
33 - **0x0** = Internal configuration space
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| D | mvebu-io-win.rst | 4 IO Window configuration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
6 The IO WIN includes a description of the address decoding configuration.
23 Returns the IO windows configuration and the number of windows of the
30 Array that include the configuration of the windows. Every window/entry is
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a80x0_mcbin/board/ |
| D | dram_port.c | 26 * the appropriate board DRAM configuration
50 MV_DDR_CFG_SPD, /* ddr configuration data source */
54 { /* electrical configuration */
55 { /* memory electrical configuration */
67 { /* phy electrical configuration */
81 { /* mac electrical configuration */
112 * configuration located on non volatile storage
125 /* select SPD memory page 0 to access DRAM configuration */ in plat_marvell_dram_update_topology()
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a80x0_puzzle/board/ |
| D | dram_port.c | 32 * the appropriate board DRAM configuration
56 MV_DDR_CFG_SPD, /* ddr configuration data source */
60 { /* electrical configuration */
61 { /* memory electrical configuration */
73 { /* phy electrical configuration */
87 { /* mac electrical configuration */
121 * configuration located on non volatile storage
134 /* select SPD memory page 0 to access DRAM configuration */ in plat_marvell_dram_update_topology()
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| /trusted-firmware-a-3.7.0/plat/marvell/octeontx/otx2/t91/t9130/board/ |
| D | dram_port.c | 26 * the appropriate board DRAM configuration
59 MV_DDR_CFG_SPD, /* ddr configuration data src */
63 { /* electrical configuration */
64 { /* memory electrical configuration */
78 { /* phy electrical configuration */
92 { /* mac electrical configuration */
136 * configuration located on non volatile storage
151 /* select SPD memory page 0 to access DRAM configuration */ in plat_marvell_dram_update_topology()
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| /trusted-firmware-a-3.7.0/plat/marvell/armada/a8k/a80x0/board/ |
| D | dram_port.c | 32 * the appropriate board DRAM configuration
60 MV_DDR_CFG_SPD, /* ddr configuration data source */
64 { /* electrical configuration */
65 { /* memory electrical configuration */
77 { /* phy electrical configuration */
91 { /* mac electrical configuration */
125 * configuration located on non volatile storage
140 /* select SPD memory page 0 to access DRAM configuration */ in plat_marvell_dram_update_topology()
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| /trusted-firmware-a-3.7.0/plat/brcm/board/common/ |
| D | cmn_sec.c | 21 ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__); in plat_tz_master_default_cfg()
27 ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__); in plat_tz_sdio_ns_master_set()
33 ERROR("%s: TZ CONFIGURATION NOT SET!!!\n", __func__); in plat_tz_usb_ns_master_set()
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| /trusted-firmware-a-3.7.0/include/drivers/ |
| D | spi_nand.h | 22 /* Configuration register */
32 /* Flags for specific configuration */
46 * configuration.
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| /trusted-firmware-a-3.7.0/include/drivers/brcm/ |
| D | chimp_nv_defs.h | 261 #define BNX_DIR_DESC_CCM "Comprehensive Configuration Management"
262 /* 0x14 PCI-IDs, PCI-related configuration properties */
265 #define BNX_DIR_DESC_PCI_CFG "PCIe Configuration Data"
279 #define BNX_DIR_DESC_ISCSI_BOOT_CFG "iSCSI Boot Configuration Data"
286 BNX_DIR_TYPE_SHARED_CFG = 40, /* 0x28 shared configuration block */
288 #define BNX_DIR_DESC_SHARED_CFG "Shared Configuration Data"
289 BNX_DIR_TYPE_PORT_CFG = 41, /* 0x29 port configuration block */
291 #define BNX_DIR_DESC_PORT_CFG "Port Configuration Data"
292 BNX_DIR_TYPE_FUNC_CFG = 42, /* 0x2A func configuration block */
294 #define BNX_DIR_DESC_FUNC_CFG "Function Configuration Data"
[all …]
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| /trusted-firmware-a-3.7.0/plat/xilinx/versal/ |
| D | versal_ipi.c | 17 /* versal ipi configuration table */
69 /* versal_ipi_config_table_init() - Initialize versal IPI configuration data.
70 * @ipi_config_table: IPI configuration table.
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| /trusted-firmware-a-3.7.0/plat/xilinx/versal_net/ |
| D | versal_net_ipi.c | 16 /* versal_net ipi configuration table */
68 /* versal_net_ipi_config_table_init() - Initialize versal_net IPI configuration
70 * @ipi_config_table: IPI configuration table.
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| /trusted-firmware-a-3.7.0/docs/design/ |
| D | reset-design.rst | 6 integrator can tailor this code to the system configuration to some extent,
22 configuration, some of these steps might be unnecessary. The following sections
103 In this configuration, the platform's Trusted Boot Firmware must ensure that
115 It allows the Arm FVP port to support the ``RESET_TO_BL31`` configuration, in
123 Juno port doesn't support the ``RESET_TO_BL31`` configuration.
125 The ``RESET_TO_BL31`` configuration requires some additions and changes in the
131 In this configuration, BL31 uses the same reset framework and code as the one
144 In this configuration, since the CPU resets to BL31, no parameters are expected
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| /trusted-firmware-a-3.7.0/plat/allwinner/common/include/ |
| D | sunxi_def.h | 10 /* Clock configuration */
13 /* UART configuration */
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| /trusted-firmware-a-3.7.0/lib/fconf/ |
| D | fconf_dyn_cfg_getter.c | 32 * global pool and set the configuration information.
112 /* Read configuration dtb information */ in fconf_populate_dtb_registry()
115 ERROR("FCONF: Incomplete configuration property in dtb-registry.\n"); in fconf_populate_dtb_registry()
122 ERROR("FCONF: Incomplete configuration property in dtb-registry.\n"); in fconf_populate_dtb_registry()
128 ERROR("FCONF: Incomplete configuration property in dtb-registry.\n"); in fconf_populate_dtb_registry()
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