1 /* 2 * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DRIVERS_SPI_NAND_H 8 #define DRIVERS_SPI_NAND_H 9 10 #include <drivers/nand.h> 11 #include <drivers/spi_mem.h> 12 13 #define SPI_NAND_OP_GET_FEATURE 0x0FU 14 #define SPI_NAND_OP_SET_FEATURE 0x1FU 15 #define SPI_NAND_OP_READ_ID 0x9FU 16 #define SPI_NAND_OP_LOAD_PAGE 0x13U 17 #define SPI_NAND_OP_RESET 0xFFU 18 #define SPI_NAND_OP_READ_FROM_CACHE 0x03U 19 #define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU 20 #define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU 21 22 /* Configuration register */ 23 #define SPI_NAND_REG_CFG 0xB0U 24 #define SPI_NAND_CFG_ECC_EN BIT(4) 25 #define SPI_NAND_CFG_QE BIT(0) 26 27 /* Status register */ 28 #define SPI_NAND_REG_STATUS 0xC0U 29 #define SPI_NAND_STATUS_BUSY BIT(0) 30 #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) 31 32 /* Flags for specific configuration */ 33 #define SPI_NAND_HAS_QE_BIT BIT(0) 34 35 struct spinand_device { 36 struct nand_device *nand_dev; 37 struct spi_mem_op spi_read_cache_op; 38 uint32_t flags; 39 uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ 40 }; 41 42 int spi_nand_init(unsigned long long *size, unsigned int *erase_size); 43 44 /* 45 * Platform can implement this to override default SPI-NAND instance 46 * configuration. 47 * 48 * @device: target SPI-NAND instance. 49 * Return 0 on success, negative value otherwise. 50 */ 51 int plat_get_spi_nand_data(struct spinand_device *device); 52 53 #endif /* DRIVERS_SPI_NAND_H */ 54
