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/Zephyr-latest/tests/drivers/clock_control/adsp_clock/src/
Dmain.c10 static void check_clocks(struct adsp_cpu_clock_info *clocks, uint32_t freq_idx) in check_clocks() argument
16 zassert_equal(clocks[i].current_freq, freq_idx, ""); in check_clocks()
22 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
24 zassert_not_null(clocks, ""); in ZTEST()
27 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
30 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_HPRO); in ZTEST()
34 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_WOVCRO); in ZTEST()
40 struct adsp_cpu_clock_info *clocks = adsp_cpu_clocks_get(); in ZTEST() local
43 zassert_not_null(clocks, ""); in ZTEST()
47 check_clocks(clocks, ADSP_CPU_CLOCK_FREQ_LPRO); in ZTEST()
[all …]
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h3 * @brief Clocks Devicetree macro public API header file.
20 * @defgroup devicetree-clocks Devicetree Clocks API
26 * @brief Test if a node has a clocks phandle-array property at a given index
28 * This expands to 1 if the given index is valid clocks property phandle-array index.
34 * clocks = <...>, <...>;
38 * clocks = <...>;
48 * @param node_id node identifier; may or may not have any clocks property
49 * @param idx index of a clocks property phandle-array whose existence to check
53 DT_PROP_HAS_IDX(node_id, clocks, idx)
58 * This expands to 1 if the name is available as clocks-name array property cell.
[all …]
/Zephyr-latest/dts/arm/raspberrypi/rpi_pico/
Drp2350.dtsi42 clocks {
45 clocks = <&pll_sys>;
54 clocks = <&pll_sys>;
62 clocks = <&pll_sys>;
70 clocks = <&pll_sys>;
78 clocks = <&pll_sys>;
86 clocks = <&xosc>;
94 clocks = <&pll_sys>;
102 clocks = <&pll_usb>;
110 clocks = <&pll_usb>;
[all …]
Drp2040.dtsi46 clocks {
49 clocks = <&pll_sys>;
58 clocks = <&pll_sys>;
66 clocks = <&pll_sys>;
74 clocks = <&pll_sys>;
82 clocks = <&xosc>;
90 clocks = <&pll_sys>;
98 clocks = <&pll_usb>;
106 clocks = <&pll_usb>;
114 clocks = <&pll_usb>;
[all …]
/Zephyr-latest/dts/arm/silabs/
Defr32bg27.dtsi12 clocks {
16 clocks = <&hfxo>;
21 clocks = <&hfrcodpll>;
26 clocks = <&em01grpaclk>;
64 clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
69 clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
74 clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
79 clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
84 clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
89 clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
[all …]
Defr32bg22.dtsi12 clocks {
16 clocks = <&em01grpaclk>;
54 clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
63 clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
68 clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
73 clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
78 clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
83 clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
89 clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
Defr32xg23.dtsi20 clocks {
24 clocks = <&hfxo>;
29 clocks = <&hfrcodpll>;
34 clocks = <&hfrcodpll>;
39 clocks = <&sysclk>;
46 clocks = <&hclk>;
53 clocks = <&pclk>;
60 clocks = <&hclk>;
67 clocks = <&sysclk>;
74 clocks = <&hfrcodpll>;
[all …]
Defr32mg24.dtsi20 clocks {
24 clocks = <&hfxo>;
29 clocks = <&hfrcodpll>;
34 clocks = <&hfrcodpll>;
39 clocks = <&sysclk>;
46 clocks = <&hclk>;
53 clocks = <&pclk>;
60 clocks = <&hclk>;
67 clocks = <&sysclk>;
74 clocks = <&hfrcodpll>;
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsamd20.dtsi21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
39 clocks = <&gclk 0x16>, <&pm 0x20 14>;
48 clocks = <&gclk 26>, <&pm 0x20 18>;
54 clocks = <&gclk 0xd>, <&pm 0x20 2>;
60 clocks = <&gclk 0xe>, <&pm 0x20 3>;
66 clocks = <&gclk 0xf>, <&pm 0x20 4>;
72 clocks = <&gclk 0x10>, <&pm 0x20 5>;
78 clocks = <&gclk 0x11>, <&pm 0x20 6>;
84 clocks = <&gclk 0x12>, <&pm 0x20 7>;
[all …]
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
46 clocks = <&gclk 26>, <&mclk 0x1c 7>;
58 clocks = <&gclk 32>, <&mclk 0x1c 12>;
64 clocks = <&gclk 18>, <&mclk 0x1c 0>;
70 clocks = <&gclk 19>, <&mclk 0x1c 1>;
76 clocks = <&gclk 20>, <&mclk 0x1c 2>;
82 clocks = <&gclk 21>, <&mclk 0x1c 3>;
88 clocks = <&gclk 22>, <&mclk 0x1c 4>;
94 clocks = <&gclk 24>, <&mclk 0x20 1>;
[all …]
Dsamd21.dtsi41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
50 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
74 clocks = <&gclk 27>, <&pm 0x20 10>;
86 clocks = <&gclk 33>, <&pm 0x20 18>;
92 clocks = <&gclk 0x14>, <&pm 0x20 2>;
98 clocks = <&gclk 0x15>, <&pm 0x20 3>;
104 clocks = <&gclk 0x16>, <&pm 0x20 4>;
110 clocks = <&gclk 0x17>, <&pm 0x20 5>;
116 clocks = <&gclk 0x18>, <&pm 0x20 6>;
[all …]
Dsame70.dtsi70 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
87 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
98 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
120 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
130 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
156 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
164 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
[all …]
Dsam4e.dtsi64 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
73 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
82 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
100 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
109 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
120 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
132 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
140 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
148 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
156 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
[all …]
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay7 /* Clocks clean up config
27 /delete-property/ clocks;
32 /delete-property/ clocks;
55 clocks = <&clk_hsi>;
60 clocks = <&pll>;
67 /delete-property/ clocks;
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
80 clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00100000>,
Dl4_i2c1_hsi_lptim1_lse.overlay7 /* Clocks clean up config
32 /delete-property/ clocks;
37 /delete-property/ clocks;
60 clocks = <&clk_hsi>;
65 clocks = <&pll>;
73 /delete-property/ clocks;
74 /* an extra clock at index 2 to check if switching clocks works */
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dl4_i2c1_sysclk_lptim1_lsi.overlay7 /* Clocks clean up config
32 /delete-property/ clocks;
37 /delete-property/ clocks;
60 clocks = <&clk_hsi>;
65 clocks = <&pll>;
73 /delete-property/ clocks;
74 /* an extra clock at index 2 to check if switching clocks works */
75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dg4_i2c1_hsi_adc1_pllp.overlay7 /* Clocks clean up config
27 /delete-property/ clocks;
32 /delete-property/ clocks;
51 clocks = <&clk_hsi>;
56 clocks = <&pll>;
63 /delete-property/ clocks;
64 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
71 clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>,
Df0_i2c1_hsi.overlay7 /* Clocks clean up config
34 /delete-property/ clocks;
39 /delete-property/ clocks;
56 clocks = <&clk_hsi>;
61 clocks = <&pll>;
66 /delete-property/ clocks;
67 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
Df3_i2c1_hsi.overlay7 /* Clocks clean up config
34 /delete-property/ clocks;
39 /delete-property/ clocks;
56 clocks = <&clk_hsi>;
61 clocks = <&pll>;
66 /delete-property/ clocks;
67 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
Dg0_i2c1_sysclk_lptim1_lsi.overlay7 /* Clocks clean up config
27 /delete-property/ clocks;
32 /delete-property/ clocks;
55 clocks = <&clk_hsi>;
60 clocks = <&pll>;
67 /delete-property/ clocks;
68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay7 /* Clocks clean up config
35 /delete-property/ clocks;
40 /delete-property/ clocks;
69 clocks = <&clk_hse>;
74 clocks = <&clk_hse>;
84 /delete-property/ clocks;
85 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
93 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
99 clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>,
/Zephyr-latest/samples/boards/st/mco/boards/
Dnucleo_f446ze.overlay7 clocks = <&clk_hse>;
14 /* clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>; */
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>;
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>;*/
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
Dnucleo_f411re.overlay7 clocks = <&clk_hse>;
14 clocks = <&rcc STM32_SRC_HSI MCO1_SEL(0)>;
15 /* clocks = <&rcc STM32_SRC_LSE MCO1_SEL(1)>; */
16 /* clocks = <&rcc STM32_SRC_HSE MCO1_SEL(2)>; */
17 /* clocks = <&rcc STM32_SRC_PLL_P MCO1_SEL(3)>; */
25 clocks = <&rcc STM32_SRC_PLLI2S_R MCO2_SEL(1)>;
/Zephyr-latest/dts/arm/nuvoton/
Dm46x.dtsi92 clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_CLKSEL1_UART0SEL_HIRC
102 clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_CLKSEL1_UART1SEL_HIRC
112 clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_CLKSEL3_UART2SEL_HIRC
122 clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_CLKSEL3_UART3SEL_HIRC
132 clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_CLKSEL3_UART4SEL_HIRC
142 clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_CLKSEL3_UART5SEL_HIRC
152 clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_CLKSEL3_UART6SEL_HIRC
162 clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_CLKSEL3_UART7SEL_HIRC
172 clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_CLKSEL2_UART8SEL_HIRC
182 clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_CLKSEL2_UART9SEL_HIRC
[all …]
/Zephyr-latest/dts/arm/infineon/cat1a/
Dsystem_clocks.dtsi10 clocks {
24 clocks = <&clk_imo>;
32 clocks = <&clk_imo>;
40 clocks = <&clk_imo>;
48 clocks = <&clk_imo>;
56 clocks = <&clk_imo>;
81 clocks = <&fll0>;
90 clocks = <&path_mux1>;
99 clocks = <&path_mux2>;
108 clocks = <&path_mux3>;
[all …]

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