| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/ |
| D | system_clocks.dtsi | 14 #clock-cells = <0>;
15 compatible = "fixed-clock";
16 clock-frequency = <8000000>;
22 #clock-cells = <0>;
23 compatible = "fixed-factor-clock";
30 #clock-cells = <0>;
31 compatible = "fixed-factor-clock";
38 #clock-cells = <0>;
39 compatible = "fixed-factor-clock";
46 #clock-cells = <0>;
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| /Zephyr-Core-3.6.0/dts/bindings/clock/ |
| D | st,stm32-rcc.yaml | 5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
27 Specifying a gated clock:
29 To specify a gated clock, a peripheral should define a "clocks" property encoded
38 control the peripheral clock in that bus register.
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| D | litex,clkout.yaml | 7 LiteX Mixed Mode Clock Manager clock output binding
13 "#clock-cells":
17 Number of cells in a clock specifier;
18 Typically 0 for nodes with a single clock output
19 and 1 for nodes with multiple clock outputs.
22 clock-output-names:
26 string of clock output signal name.
28 litex,clock-frequency:
32 default frequency in Hz for clock output
34 litex,clock-phase:
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| D | st,stm32wba-rcc.yaml | 5 STM32 Reset and Clock controller node.
6 This node is in charge of system clock ('SYSCLK') source selection and controlling
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
13 Core clock frequency should also be defined, using "clock-frequency" property.
15 Core clock frequency = SYSCLK / AHB prescaler
22 clock-frequency = <DT_FREQ_M(40)>; /* = SYSCLK / AHB prescaler */
28 Specifying a gated clock:
30 To specify a gated clock, a peripheral should define a "clocks" property encoded
39 control the peripheral clock in that bus register.
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| D | pwm-clock.yaml | 5 An external clock signal driven by a PWM pin.
7 The devicetree must define a clock node:
11 compatible = "pwm-clock";
12 #clock-cells = <1>;
16 This will create a device node with a clock-controller
18 clock signals at 1MHz. Note that the PWM_HZ() macro converts the
20 errors if the clock frequency is not an integer number of nanoseconds.
21 The clock frequency can be explicitly set using the clock-frequency
28 compatible: "pwm-clock"
30 include: [clock-controller.yaml, base.yaml]
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| D | fixed-factor-clock.yaml | 4 description: Generic fixed factor clock provider
6 compatible: "fixed-factor-clock"
8 include: clock-controller.yaml
11 clock-div:
13 description: fixed clock divider
15 clock-mult:
17 description: fixed clock multiplier
21 description: input clock source
23 "#clock-cells":
|
| D | microchip,xec-pcr.yaml | 4 description: Microchip XEC Power Clock Reset and VBAT register (PCR)
8 include: [clock-controller.yaml, pinctrl-device.yaml, base.yaml]
14 core-clock-div:
17 description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
19 slow-clock-div:
22 PWM and TACH clock domain divided down from 48 MHz AHB clock. The
28 description: 32 KHz clock source for PLL
33 description: 32 KHz clock source for peripherals
43 32KHz clock monitor minimum valid 32KHz period in 48MHz units
49 32KHz clock monitor maximum valid 32KHz period in 48MHz units
[all …]
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| D | st,stm32g0-pll-clock.yaml | 7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to I2S
15 f(PLL_Q) = f(VCO clock) / PLLQ --> to RNG
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g0-pll-clock"
24 include: [clock-controller.yaml, base.yaml]
27 "#clock-cells":
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| D | st,stm32l4-pll-clock.yaml | 10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLSAI3CLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48M1CLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
25 compatible: "st,stm32l4-pll-clock"
27 include: [clock-controller.yaml, base.yaml]
30 "#clock-cells":
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| D | st,stm32wb-pll-clock.yaml | 10 These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
12 clock in this acceptable range.
14 Each PLL can have up to 3 output clocks and for each output clock, the
17 f(PLL_P) = f(VCO clock) / PLLP --> PLLPCLK
18 f(PLL_Q) = f(VCO clock) / PLLQ --> PLLQCLK
19 f(PLL_R) = f(VCO clock) / PLLR --> PLLRCLK (System Clock)
21 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
27 compatible: "st,stm32wb-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
32 "#clock-cells":
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| D | st,stm32g4-pll-clock.yaml | 7 It can take one of clk_hse or clk_hsi as input clock, with
9 clock in this acceptable range.
11 PLL can have up to 3 output clocks and for each output clock, the
14 f(PLL_P) = f(VCO clock) / PLLP --> to ADC
15 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48MCLK (for USB, RNG)
16 f(PLL_R) = f(VCO clock) / PLLR --> PLLCLK (System Clock)
18 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22 compatible: "st,stm32g4-pll-clock"
25 - name: st,stm32l4-pll-clock.yaml
37 Division factor for PLL input clock
|
| D | st,stm32f7-pll-clock.yaml | 7 Takes one of clk_hse or clk_hsi as input clock.
9 Up to 2 output clocks could be supported and for each output clock, the
12 f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
13 f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
15 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
18 compatible: "st,stm32f7-pll-clock"
20 include: [clock-controller.yaml, base.yaml]
23 "#clock-cells":
33 Division factor for the PLL input clock
|
| D | st,stm32h7-rcc.yaml | 5 STM32 Reset and Clock controller node for STM32H7 devices
6 This node is in charge of system clock ('SYSCLK') source selection and
7 System Clock Generation.
9 Configuring STM32 Reset and Clock controller node:
11 System clock source should be selected amongst the clock nodes available in "clocks"
14 "clock-frequency" property.
20 clock-frequency = <DT_FREQ_M(480)>; /* SYSCLK runs at 480MHz */
33 include: [clock-controller.yaml, base.yaml]
39 "#clock-cells":
42 clock-frequency:
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| D | st,stm32wba-pll-clock.yaml | 9 This PLL could take one of clk_hse or clk_hsi as input clock, with
11 clock in this acceptable range.
13 PLL1 can have up to 3 output clocks and for each output clock, the
16 f(PLL_P) = f(VCO clock) / PLLP
17 f(PLL_Q) = f(VCO clock) / PLLQ
18 f(PLL_R) = f(VCO clock) / PLLR
20 with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
27 compatible: "st,stm32wba-pll-clock"
29 include: [clock-controller.yaml, base.yaml]
33 "#clock-cells":
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| /Zephyr-Core-3.6.0/drivers/timer/ |
| D | Kconfig.nrf_xrtc | 8 prompt "Clock startup policy"
14 System clock source is initiated but does not wait for clock readiness.
15 When this option is picked, system clock may not be ready when code relying
22 System clock source initialization waits until clock is available. In some
23 systems, clock initially runs from less accurate source which has faster
24 startup time and then seamlessly switches to the target clock source when
25 it is ready. When this option is picked, system clock is available after
26 system clock driver initialization but it may be less accurate. Option is
27 equivalent to waiting for stability if clock source does not have
33 System clock source initialization waits until clock is stable. When this
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|
| /Zephyr-Core-3.6.0/dts/bindings/usb/uac2/ |
| D | zephyr,uac2-clock-source.yaml | 4 description: USB Audio Class 2 Clock Source entity
6 compatible: "zephyr,uac2-clock-source"
9 clock-type:
13 Clock Type indicating whether the Clock Source represents an external
14 clock or an internal clock with either fixed frequency, variable
25 True if clock is synchronized to USB Start of Frame. False if clock is
26 free running. External clock must be free running.
30 description: Clock Frequency Control capabilities
37 description: Clock Validity Control capabilities
44 Input or Output Terminal associated with this Clock Source. Set if clock
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|
| /Zephyr-Core-3.6.0/dts/riscv/starfive/ |
| D | starfive_jh7100_clk.dtsi | 9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-frequency = <125000000>;
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
17 clock-frequency = <125000000>;
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <100000000>;
27 #clock-cells = <0>;
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| /Zephyr-Core-3.6.0/dts/arm/rpi_pico/ |
| D | rp2040.dtsi | 10 #include <zephyr/dt-bindings/clock/rpi_pico_clock.h>
39 compatible = "raspberrypi,pico-clock";
41 clock-names = "pll_sys";
42 clock-frequency = <125000000>;
43 #clock-cells = <0>;
48 compatible = "raspberrypi,pico-clock";
50 clock-names = "pll_sys";
51 clock-frequency = <125000000>;
52 #clock-cells = <0>;
56 compatible = "raspberrypi,pico-clock";
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| /Zephyr-Core-3.6.0/soc/arm/atmel_sam0/common/ |
| D | Kconfig.samd2x | 16 This can then be selected as the main clock reference for the SOC.
22 This can then be selected as the main clock reference for the SOC.
25 bool "External 32.768 kHz clock source"
27 Enable the external 32.768 kHz clock source at startup.
28 This can then be selected as the main clock reference for the SOC.
31 bool "External 32.768 kHz clock is a crystal oscillator"
35 Enable the crystal oscillator (if disabled, expect a clock signal on
39 bool "External 0.4..32 MHz clock source"
41 Enable the external 0.4..32 MHz clock source at startup.
42 This can then be selected as the main clock reference for the SOC.
[all …]
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| /Zephyr-Core-3.6.0/soc/arm/nxp_kinetis/k8x/ |
| D | Kconfig.soc | 45 int "Freescale K8x core clock divider"
48 This option specifies the divide value for the K8x processor core clock
49 from the system clock.
52 int "Freescale K8x bus clock divider"
55 This option specifies the divide value for the K8x bus clock from the
56 system clock.
59 int "Freescale K8x FlexBus clock divider"
62 This option specifies the divide value for the K8x FlexBus clock from the
63 system clock.
66 int "Freescale K8x flash clock divider"
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| /Zephyr-Core-3.6.0/dts/bindings/pwm/ |
| D | microchip,xec-pwmbbled.yaml | 27 clock-select:
31 Clock source selection: 32 KHz is available in deep sleep.
32 - PWM_BBLED_CLK_AHB: Clock source is the PLL based AHB clock
33 - PWM_BBLED_CLK_SLOW: Clock source is the PLL based PCR slow clock
34 - PWM_BBLED_CLK_32K: Clock source is the 32KHz domain
52 BBLED has two clock inputs.
53 - Main system clock (48MHz)
54 - 32KHz Core clock (32.768KHz)
55 When BBLED enter into Suspend state, 48MHz clock will be switched off by
56 PCR(Power, Clock and Reset) block. But 32KHz Core clock will be available to BBLED.
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| /Zephyr-Core-3.6.0/include/zephyr/drivers/ |
| D | clock_control.h | 1 /* clock_control.h - public clock controller driver API */
11 * @brief Public Clock Control APIs
18 * @brief Clock Control Interface
19 * @defgroup clock_control_interface Clock Control Interface
36 /* Clock control API */
38 /* Used to select all subsystem of a clock controller */
42 * @brief Current clock status.
52 * clock_control_subsys_t is a type to identify a clock controller sub-system.
53 * Such data pointed is opaque and relevant only to the clock controller
59 * clock_control_subsys_rate_t is a type to identify a clock
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| /Zephyr-Core-3.6.0/soc/arm/nxp_imx/mcimx7_m4/ |
| D | soc.c | 13 /* Initialize clock. */
20 * Note : The WDOG clock Root is shared by all the 4 WDOGs, in SOC_ClockInit()
39 /* Enable clock gate for IP bridge and IO mux */ in SOC_ClockInit()
46 /* Enable clock gate for RDC */ in SOC_ClockInit()
62 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
69 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
76 /* Enable gpio clock gate */ in nxp_mcimx7_gpio_config()
90 /* Select clock derived from OSC clock(24M) */ in nxp_mcimx7_uart_config()
92 /* Enable uart clock */ in nxp_mcimx7_uart_config()
97 * So we need UART clock all the time in nxp_mcimx7_uart_config()
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| /Zephyr-Core-3.6.0/boards/arm/cy8cproto_063_ble/ |
| D | cy8cproto_063_ble.dts | 91 /* System clock configuration */
94 clock-frequency = <100000000>;
98 clock-div = <1>;
102 /* CM4 core clock = 100MHz
103 * &fll clock-frequency / &clk_hf0 clock-div / &clk_fast clock-div = 100MHz / 1 / 1 = 100MHz
106 clock-div = <1>;
109 /* CM0+ core clock = 50MHz
110 * &fll clock-frequency / &clk_hf0 clock-div / &clk_slow clock-div = 100MHz / 1 / 2 = 50MHz
113 clock-div = <2>;
116 /* PERI core clock = 100MHz
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| /Zephyr-Core-3.6.0/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/ |
| D | testcase.yaml | 1 # Note: On most ST development boards, external clock "HSE 8MHz" is provided thanks to ST-Link
12 drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_48_msi_4:
21 drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hsi_16:
30 drivers.clock.stm32_clock_configuration.common_core.sysclksrc_hsi_16:
41 drivers.clock.stm32_clock_configuration.common_core.sysclksrc_msi_48:
52 drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_hse_8.fixup:
64 drivers.clock.stm32_clock_configuration.common_core.l4_l5.sysclksrc_pll_64_hse_8.fixup:
76 drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_pll_64_hse_8:
84 drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_2:
89 drivers.clock.stm32_clock_configuration.common_core.g0.sysclksrc_hsi_g0_16_div_4:
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