1# Copyright (c) 2021, Linaro ltd
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  STM32WB and STM32WL PLL node.
6
7  It can be used to describe 2 different PLLs: PLL, PLLSAI1.
8  Only main PLL is supported for now.
9
10  These PLLs could take one of clk_hse, clk_hsi or clk_msi as input clock, with
11  an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
12  clock in this acceptable range.
13
14  Each PLL can have up to 3 output clocks and for each output clock, the
15  frequency can be computed with the following formulae:
16
17    f(PLL_P) = f(VCO clock) / PLLP  --> PLLPCLK
18    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLLQCLK
19    f(PLL_R) = f(VCO clock) / PLLR  --> PLLRCLK (System Clock)
20
21      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
22
23  The PLL output frequency must not exceed:
24          - 64 MHz on STM32WB
25          - 62 MHz on STM32WL
26
27compatible: "st,stm32wb-pll-clock"
28
29include: [clock-controller.yaml, base.yaml]
30
31properties:
32  "#clock-cells":
33    const: 0
34
35  clocks:
36    required: true
37
38  div-m:
39    type: int
40    required: true
41    description: |
42        Main PLL division factor for PLL input clock
43        Valid range: 1 - 8
44
45  mul-n:
46    type: int
47    required: true
48    description: |
49        Main PLL multiplication factor for VCO
50        Valid range: 6 - 127
51
52  div-p:
53    type: int
54    description: |
55        Main PLL division factor for PLLPCLK
56        Valid range: 2 - 32
57
58  div-q:
59    type: int
60    description: |
61        Main PLL division factor for PLLQCLK
62        Valid range: 2 - 8
63
64  div-r:
65    type: int
66    required: true
67    description: |
68        Main PLL division factor for PLLRCLK (system clock)
69        Valid range: 2 - 8
70