1# Copyright (c) 2023, STMicroelectronics
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  PLL node binding for STM32WBA devices
6
7  It can be used to describe PLL1
8
9  This PLL could take one of clk_hse or clk_hsi as input clock, with
10  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
11  clock in this acceptable range.
12
13  PLL1 can have up to 3 output clocks and for each output clock, the
14  frequency can be computed with the following formula:
15
16    f(PLL_P) = f(VCO clock) / PLLP
17    f(PLL_Q) = f(VCO clock) / PLLQ
18    f(PLL_R) = f(VCO clock) / PLLR
19
20      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
21
22  Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
23        it is recommended to configure the VCO to the lowest frequency.
24
25  The PLL output frequency must not exceed 100 MHz.
26
27compatible: "st,stm32wba-pll-clock"
28
29include: [clock-controller.yaml, base.yaml]
30
31properties:
32
33  "#clock-cells":
34    const: 0
35
36  clocks:
37    required: true
38
39  div-m:
40    type: int
41    required: true
42    description: |
43        Prescaler for PLLx
44        input clock
45        Valid range: 1 - 8
46
47  mul-n:
48    type: int
49    required: true
50    description: |
51        PLLx multiplication factor for VCO
52        Valid range: 4 - 512
53
54  div-q:
55    type: int
56    description: |
57        PLLx DIVQ division factor
58        Valid range: 1 - 128
59
60  div-r:
61    type: int
62    required: true
63    description: |
64        PLLx DIVR division factor
65        Valid range: 1 - 128
66