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Searched +full:clksys +full:- +full:prescaler (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/dts/bindings/clock/
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
26 slow-clock:
35 clksys-prescaler:
39 - 1
40 - 2
41 - 4
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/Zephyr-latest/boards/st/nucleo_wb05kz/
Dnucleo_wb05kz.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb0/stm32wb05kzvx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "STMicroelectronics STM32WB05KZ-NUCLEO board";
16 compatible = "st,stm32wb05kz-nucleo";
18 #address-cells = <1>;
19 #size-cells = <1>;
23 zephyr,shell-uart = &usart1;
26 zephyr,bt-c2h-uart = &usart1;
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/Zephyr-latest/boards/st/nucleo_wb09ke/
Dnucleo_wb09ke.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include <st/wb0/stm32wb09kevx-pinctrl.dtsi>
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
15 model = "STMicroelectronics STM32WB09KE-NUCLEO board";
16 compatible = "st,stm32wb09ke-nucleo";
18 #address-cells = <1>;
19 #size-cells = <1>;
23 zephyr,shell-uart = &usart1;
26 zephyr,bt-c2h-uart = &usart1;
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/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wb0.c4 * SPDX-License-Identifier: Apache-2.0
43 # error slow-clock source is not enabled
53 # error Invalid device selected as slow-clock
66 "clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
108 * NOTE: (size - 1) is required to get the correct count, in measure_lsi_frequency()
113 (CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1)); in measure_lsi_frequency()
137 * LSI calibration counts the amount of 16MHz clock half-periods that in measure_lsi_frequency()
140 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods in measure_lsi_frequency()
155 * = ------------------------------------------------ in measure_lsi_frequency()
163 * = ------------------------------------------------ in measure_lsi_frequency()
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