4  * SPDX-License-Identifier: Apache-2.0
43 #		error slow-clock source is not enabled
53 #		error Invalid device selected as slow-clock
66 	"clksys-prescaler cannot be 64 when SYSCLK source is Direct HSE");
108 	 * NOTE: (size - 1) is required to get the correct count,  in measure_lsi_frequency()
113 		(CONFIG_STM32WB0_LSI_MEASUREMENT_WINDOW - 1));  in measure_lsi_frequency()
137 	 * LSI calibration counts the amount of 16MHz clock half-periods that  in measure_lsi_frequency()
140 	 * @p fast_clock_cycles_elapsed is the number of 16MHz clock half-periods  in measure_lsi_frequency()
155 	 *      = ------------------------------------------------  in measure_lsi_frequency()
163 	 *      = ------------------------------------------------  in measure_lsi_frequency()
167 	 *      = -----------------------------------------------------  in measure_lsi_frequency()
170 	 * NOTE: The division must be performed first to avoid 32-bit overflow.  in measure_lsi_frequency()
188 			r = -ENOTSUP;  in enabled_clock()
193 			r = -ENOTSUP;  in enabled_clock()
203 		return -ENOTSUP;  in enabled_clock()
213 	const mem_addr_t reg = RCC_REG(pclken->bus);  in stm32_clock_control_on()
217 	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {  in stm32_clock_control_on()
219 		return -ENOTSUP;  in stm32_clock_control_on()
222 	sys_set_bits(reg, pclken->enr);  in stm32_clock_control_on()
237 	const mem_addr_t reg = RCC_REG(pclken->bus);  in stm32_clock_control_off()
240 	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {  in stm32_clock_control_off()
242 		return -ENOTSUP;  in stm32_clock_control_off()
245 	sys_clear_bits(reg, pclken->enr);  in stm32_clock_control_off()
255 	const uint32_t shift = STM32_CLOCK_SHIFT_GET(pclken->enr);  in stm32_clock_control_configure()
256 	mem_addr_t reg = RCC_REG(STM32_CLOCK_REG_GET(pclken->enr));  in stm32_clock_control_configure()
262 	err = enabled_clock(pclken->bus);  in stm32_clock_control_configure()
268 	sys_clear_bits(reg, STM32_CLOCK_MASK_GET(pclken->enr) << shift);  in stm32_clock_control_configure()
269 	sys_set_bits(reg, STM32_CLOCK_VAL_GET(pclken->enr) << shift);  in stm32_clock_control_configure()
277 	switch (pclken->enr) {  in get_apb0_periph_clkrate()
305 		return -ENOTSUP;  in get_apb0_periph_clkrate()
308 	if (pclken->div) {  in get_apb0_periph_clkrate()
309 		*rate /= (pclken->div + 1);  in get_apb0_periph_clkrate()
318 	switch (pclken->enr) {  in get_apb1_periph_clkrate()
366 	/* ADC has two enable bits - accept all combinations. */  in get_apb1_periph_clkrate()
391 		return -ENOTSUP;  in get_apb1_periph_clkrate()
394 	if (pclken->div) {  in get_apb1_periph_clkrate()
395 		*rate /= (pclken->div + 1);  in get_apb1_periph_clkrate()
417 	/* Obtain SYSCLK frequency by checking which source drives high-speed clock tree.  in stm32_clock_control_get_subsys_rate()
418 	 * If Direct HSE is enabled, the high-speed tree is clocked by HSE @ 32MHz.  in stm32_clock_control_get_subsys_rate()
419 	 * Otherwise, the high-speed tree is clocked by the RC64MPLL clock @ 64MHz.  in stm32_clock_control_get_subsys_rate()
421 	 * NOTE: it is NOT possible to use the usual 'SystemCoreClock * Prescaler' approach on  in stm32_clock_control_get_subsys_rate()
422 	 * STM32WB0 because the prescaler configuration is not affected by input clock variation:  in stm32_clock_control_get_subsys_rate()
431 	/* Obtain CLK_SYS (AHB0) frequency by using the CLKSYSDIV prescaler value.  in stm32_clock_control_get_subsys_rate()
434 	 * and can be used regardless of which source is driving the high-speed clock tree.  in stm32_clock_control_get_subsys_rate()
436 	 * NOTE: the prescaler value must be interpreted as if source clock is 64MHz, regardless  in stm32_clock_control_get_subsys_rate()
437 	 * of which source is actually driving the high-speed clock tree. This allows using the  in stm32_clock_control_get_subsys_rate()
444 	/* Obtain slow clock tree source by reading RCC_CFGR->LCOSEL.  in stm32_clock_control_get_subsys_rate()
462 	switch (pclken->bus) {  in stm32_clock_control_get_subsys_rate()
501 		return -ENOTSUP;  in stm32_clock_control_get_subsys_rate()
504 	if (pclken->div) {  in stm32_clock_control_get_subsys_rate()
505 		*rate /= (pclken->div + 1);  in stm32_clock_control_get_subsys_rate()
518 	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {  in stm32_clock_control_get_status()
520 		if ((sys_read32(RCC_REG(pclken->bus)) & pclken->enr) == pclken->enr) {  in stm32_clock_control_get_status()
527 		if (enabled_clock(pclken->bus) == 0) {  in stm32_clock_control_get_status()
576 		/* Unconditionally disable pull-up & pull-down on LSE pins */  in set_up_fixed_clock_sources()
592 /* The STM32WB0 prescaler division factor defines vary depending on
622 	/* A prescaler value of 64 is only valid when running  in kconfig_to_ll_prescaler()
652 	return -ENOMEM;  in stm32wb0_register_lsi_update_callback()
713 	 *  - 1 wait state when CLK_SYS > 32MHz (i.e., 64MHz configuration)  in stm32_clock_control_init()
714 	 *  - 0 wait states otherwise (CLK_SYS <= 32MHz)  in stm32_clock_control_init()
757 	/* Set CLK_SYS prescaler */  in stm32_clock_control_init()