Lines Matching +full:clksys +full:- +full:prescaler

2 # SPDX-License-Identifier: Apache-2.0
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17   "#clock-cells":
20   clock-frequency:
26   slow-clock:
35   clksys-prescaler:
39       - 1
40       - 2
41       - 4
42       - 8
43       - 16
44       - 32
45       - 64
47       CLK_SYS prescaler. Defines actual core clock frequency (CLK_SYS) based
51       NOTE: if the 32MHz HSE is used as SYSCLK source, the prescaler cannot
54 clock-cells:
55   - bus
56   - bits