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/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dledc_reg.h1607 * Ledc ch2 gamma ram write register.
1611 * Ledc ch2 gamma duty inc of current ram write address.This register is used to
1621 * Ledc ch2 gamma duty cycle of current ram write address.The duty will change every
1629 * Ledc ch2 gamma scale of current ram write address.This register is used to
1637 * Ledc ch2 gamma duty num of current ram write address.This register is used to
1646 * Ledc ch2 gamma ram write address register.
1650 * Ledc ch2 gamma ram write address.
1658 * Ledc ch2 gamma ram read address register.
1662 * Ledc ch2 gamma ram read address.
1670 * Ledc ch2 gamma ram read data register.
[all …]
Dledc_struct.h90 * Ledc ch2 duty change end event enable register, write 1 to enable this event.
115 * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event.
172 * Ledc ch2 duty scale update task enable register, write 1 to enable this task.
238 * Ledc ch2 signal out disable task enable register, write 1 to enable this task.
263 * Ledc ch2 overflow count reset task enable register, write 1 to enable this task.
329 * Ledc ch2 gamma restart task enable register, write 1 to enable this task.
354 * Ledc ch2 gamma pause task enable register, write 1 to enable this task.
379 * Ledc ch2 gamma resume task enable register, write 1 to enable this task.
Dsoc_etm_struct.h28 * ch2 enable
165 * ch2 set
302 * ch2 clear
Dsoc_etm_reg.h33 * ch2 enable
262 * ch2 set
491 * ch2 clear
Defuse_struct.h754 * ADC1 init code at atten0 ch2
Defuse_reg.h965 * ADC1 init code at atten0 ch2
Dmcpwm_reg.h2757 * ch2 capture value status register
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dledc_reg.h1607 * Ledc ch2 gamma ram write register.
1611 * Ledc ch2 gamma duty inc of current ram write address.This register is used to
1621 * Ledc ch2 gamma duty cycle of current ram write address.The duty will change every
1629 * Ledc ch2 gamma scale of current ram write address.This register is used to
1637 * Ledc ch2 gamma duty num of current ram write address.This register is used to
1646 * Ledc ch2 gamma ram write address register.
1650 * Ledc ch2 gamma ram write address.
1658 * Ledc ch2 gamma ram read address register.
1662 * Ledc ch2 gamma ram read address.
1670 * Ledc ch2 gamma ram read data register.
[all …]
Dledc_struct.h90 * Ledc ch2 duty change end event enable register, write 1 to enable this event.
115 * Ledc ch2 overflow count pulse event enable register, write 1 to enable this event.
172 * Ledc ch2 duty scale update task enable register, write 1 to enable this task.
238 * Ledc ch2 signal out disable task enable register, write 1 to enable this task.
263 * Ledc ch2 overflow count reset task enable register, write 1 to enable this task.
329 * Ledc ch2 gamma restart task enable register, write 1 to enable this task.
354 * Ledc ch2 gamma pause task enable register, write 1 to enable this task.
379 * Ledc ch2 gamma resume task enable register, write 1 to enable this task.
Dsoc_etm_struct.h28 * ch2 enable
165 * ch2 set
302 * ch2 clear
Dsoc_etm_reg.h33 * ch2 enable
262 * ch2 set
491 * ch2 clear
Dmcpwm_reg.h2757 * ch2 capture value status register
/hal_espressif-latest/zephyr/port/pincfgs/
Desp32c2.yml80 ch2:
Desp32c3.yml132 ch2:
Desp32c6.yml85 ch2:
Desp32.yml192 ch2:
454 ch2:
Desp32s2.yml165 ch2:
Desp32s3.yml191 ch2:
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drmt_struct.h233 uint32_t ch2: 1; member
/hal_espressif-latest/components/bt/host/bluedroid/stack/l2cap/
Dl2c_main.c106 //counter_add("l2cap.ch2.tx.bytes", p_buf->len);
107 //counter_add("l2cap.ch2.tx.pkts", 1);
254 //counter_add("l2cap.ch2.rx.bytes", l2cap_len); in l2c_rcv_acl_data()
255 //counter_add("l2cap.ch2.rx.pkts", 1); in l2c_rcv_acl_data()
/hal_espressif-latest/components/efuse/esp32c6/
Desp_efuse_table.csv188 …1_INIT_CODE_ATTEN0_CH2, EFUSE_BLK2, 233, 4, [] ADC1 init code at atten0 ch2
Desp_efuse_table.c697 {EFUSE_BLK2, 233, 4}, // [] ADC1 init code at atten0 ch2,
1603 &ADC1_INIT_CODE_ATTEN0_CH2[0], // [] ADC1 init code at atten0 ch2
/hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/
Desp32c6.yaml96 … : '', dict : '', desc: ADC1 init code at atten0 ch2, rloc: 'EFUSE_RD_SY…
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dmcpwm_reg.h2829 * ch2 capture value status register
/hal_espressif-latest/components/soc/esp32/include/soc/
Dmcpwm_reg.h2829 * ch2 capture value status register