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/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dledc_reg.h1532 * Ledc ch1 gamma ram write register.
1536 * Ledc ch1 gamma duty inc of current ram write address.This register is used to
1546 * Ledc ch1 gamma duty cycle of current ram write address.The duty will change every
1554 * Ledc ch1 gamma scale of current ram write address.This register is used to
1562 * Ledc ch1 gamma duty num of current ram write address.This register is used to
1571 * Ledc ch1 gamma ram write address register.
1575 * Ledc ch1 gamma ram write address.
1583 * Ledc ch1 gamma ram read address register.
1587 * Ledc ch1 gamma ram read address.
1595 * Ledc ch1 gamma ram read data register.
[all …]
Dledc_struct.h86 * Ledc ch1 duty change end event enable register, write 1 to enable this event.
111 * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event.
168 * Ledc ch1 duty scale update task enable register, write 1 to enable this task.
234 * Ledc ch1 signal out disable task enable register, write 1 to enable this task.
259 * Ledc ch1 overflow count reset task enable register, write 1 to enable this task.
325 * Ledc ch1 gamma restart task enable register, write 1 to enable this task.
350 * Ledc ch1 gamma pause task enable register, write 1 to enable this task.
375 * Ledc ch1 gamma resume task enable register, write 1 to enable this task.
Dsoc_etm_struct.h24 * ch1 enable
161 * ch1 set
298 * ch1 clear
Dsoc_etm_reg.h26 * ch1 enable
255 * ch1 set
484 * ch1 clear
Defuse_struct.h750 * ADC1 init code at atten0 ch1
Defuse_reg.h958 * ADC1 init code at atten0 ch1
Dmcpwm_reg.h2745 * ch1 capture value status register
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dledc_reg.h1532 * Ledc ch1 gamma ram write register.
1536 * Ledc ch1 gamma duty inc of current ram write address.This register is used to
1546 * Ledc ch1 gamma duty cycle of current ram write address.The duty will change every
1554 * Ledc ch1 gamma scale of current ram write address.This register is used to
1562 * Ledc ch1 gamma duty num of current ram write address.This register is used to
1571 * Ledc ch1 gamma ram write address register.
1575 * Ledc ch1 gamma ram write address.
1583 * Ledc ch1 gamma ram read address register.
1587 * Ledc ch1 gamma ram read address.
1595 * Ledc ch1 gamma ram read data register.
[all …]
Dledc_struct.h86 * Ledc ch1 duty change end event enable register, write 1 to enable this event.
111 * Ledc ch1 overflow count pulse event enable register, write 1 to enable this event.
168 * Ledc ch1 duty scale update task enable register, write 1 to enable this task.
234 * Ledc ch1 signal out disable task enable register, write 1 to enable this task.
259 * Ledc ch1 overflow count reset task enable register, write 1 to enable this task.
325 * Ledc ch1 gamma restart task enable register, write 1 to enable this task.
350 * Ledc ch1 gamma pause task enable register, write 1 to enable this task.
375 * Ledc ch1 gamma resume task enable register, write 1 to enable this task.
Dsoc_etm_struct.h24 * ch1 enable
161 * ch1 set
298 * ch1 clear
Dsoc_etm_reg.h26 * ch1 enable
255 * ch1 set
484 * ch1 clear
Dmcpwm_reg.h2745 * ch1 capture value status register
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Drmt_struct.h223 uint32_t ch1: 1; member
232 uint32_t ch1: 1; member
/hal_espressif-latest/zephyr/port/pincfgs/
Desp32c2.yml77 ch1:
Desp32c3.yml129 ch1:
Desp32c6.yml82 ch1:
Desp32.yml189 ch1:
451 ch1:
Desp32s2.yml162 ch1:
Desp32s3.yml188 ch1:
/hal_espressif-latest/components/efuse/esp32c6/
Desp_efuse_table.csv187 …1_INIT_CODE_ATTEN0_CH1, EFUSE_BLK2, 229, 4, [] ADC1 init code at atten0 ch1
Desp_efuse_table.c693 {EFUSE_BLK2, 229, 4}, // [] ADC1 init code at atten0 ch1,
1598 &ADC1_INIT_CODE_ATTEN0_CH1[0], // [] ADC1 init code at atten0 ch1
/hal_espressif-latest/components/bt/host/bluedroid/stack/sdp/
Dsdp_discovery.c1012 /* SDP_TRACE_DEBUG ("parent:0x%x(id:%d), ch1:0x%x(id:%d)", in add_attr()
/hal_espressif-latest/tools/esptool_py/espefuse/efuse_defs/
Desp32c6.yaml95 … : '', dict : '', desc: ADC1 init code at atten0 ch1, rloc: 'EFUSE_RD_SY…
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dmcpwm_reg.h2817 * ch1 capture value status register
/hal_espressif-latest/components/soc/esp32/include/soc/
Dmcpwm_reg.h2817 * ch1 capture value status register